// Test the reader's ability to handle undefined modules in the Verilog// input.  The reader should create "stub" references to these modules// using the union of all interfaces that are defined on the module.  Also test// the reader's ability to detect and detach empty modules which should be// created as black boxes.module empty(a, b, c);    input	    a;    input   [1:0]   b;    output	    c;endmodulemodule top();    wire            wireToA, wireToC, wireToX, wireToZ;    wire    [1:0]   busToB, busToY;    wire    [3:0]   wideBusToB, wideBusToY;        empty   designInst(.a(wireToA), .b(busToB), .c(wireToC));        stub    lowNames(.c(wireToC), .a(wireToA), .b(busToB)),            highNames(.y(busToY), .z(wireToZ), .x(wireToX));                stub    vectorInst[1:0](.y(wideBusToY), .z(wireToZ), .x(wireToX));    stub    scalarOrder(wireToA, busToB, wireToC,                         wireToX, busToY, wireToZ);                stub    vectorOrder[1:0](wireToA, wideBusToB, wireToC,                             wireToX, wideBusToY, wireToZ);   endmodule