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<?xml version="1.0" encoding="gb2312"?><!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html xmlns="http://www.w3.org/1999/xhtml"><head><meta http-equiv="Content-Type" content="text/html; charset=gb2312"/><title>BDM手冊4 turbolinux </title></head><body><center><h1>BBS 水木清華站∶精華區</h1></center><a name="top"></a>發信人: doot (ltt), 信區: Embedded <br />標 題: BDM手冊4 <br />發信站: BBS 水木清華站 (Thu Oct 26 16:19:56 2000) <br /> <br />SECTION II - On- Chip Debugging <br />What is OCD? - Hardware, Software, … <br />In the general sense, on- chip debugging is a combination of hardware and so <br />ftware, both <br />on and off the chip. The part that resides on the chip is implemented in var <br />ious ways. It <br />may be a microcode based monitor (Motorola CPU32) or hardware implemented re <br />sources <br />(IBM PPC403). There may be resources used that are available to the end- use <br />r’s code such <br />as breakpoint registers (most embedded PowerPC implementations) or dedicated <br /> hardware <br />purely used by the OCD such as instruction stuff buffers (also in embedded P <br />owerPC <br />implementations). <br />On- chip debugging does require some external hardware, however minimal it m <br />ay be. <br />There must communication between the chip and debugger host. In most cases t <br />his is via <br />a dual- row pin header and several pins on the processor. The IBM 403 family <br /> uses the <br />JTAG port pins, in addition to RESET, power sense and ground, and connects v <br />ia a 16 pin <br />dual- row header. Motorola BDM typically uses five dedicated pins (sometimes <br /> multiplexed <br />with real- time execution functions), power, ground, and at least one reset, <br /> all terminating <br />in a 10 pin dual- row header. Many of the DSP chips use a Texas Instruments <br />style <br />standard JTAG interface. Motorola has expanded the interface’s internal def <br />inition to <br />include its DSP BDM equivalent, OnCE. <br />On- chip resources are only half the story. A target system with an OCD proc <br />essor and its <br />dual- row header are useless unless you have a host to communicate with. The <br /> host runs <br />your debugger software and interfaces to the OCD header in various ways. The <br /> debugger <br />on the host implements the user interface displaying your code, processor re <br />sources, target <br />memory, etc. The hardware interface may be one of many types. The simplest i <br />s typically <br />a “wiggler”, a device that interfaces the parallel port of an IBM type PC <br />to an OCD header <br />(Software Development Systems BDM, Motorola ICD cable). This is both simple <br />and slow. <br />Other interfaces are serial port (RS- 232) to OCD converters (Cygnus), high <br />speed parallel <br />port to OCD (Macraigor Systems), ethernet to OCD (Cygnus, Macraigor Systems) <br />, ISA bus <br />card to OCD (Nohau), and others. Cost of host software runs from $49 to seve <br />ral thousand <br />dollars. The hardware typically costs from $100 to $3000 (wiggler vs. ethern <br />et interface). <br />Types of OCD <br />BDM (Motorola CPU16, CPU32, ColdFire) <br />As mentioned previously, Motorola coined the term BDM (Background Mode Debug <br />) with <br />its CPU32 family of microcontrollers. This was followed by the CPU16 family, <br /> and then <br />ColdFire. These BDMs are extremely similar. They build upon the concept of a <br /> ROM <br />monitor and have a similar command set. The core of the hardware interface c <br />onsists of a <br />serial data in, serial data out, serial clock/ breakpoint, and freeze status <br /> signal. The commands <br />are shifted into the chip serially and are 17 bits in length. The command se <br />t for the <br />CPU32 is as follows: <br /> RAREG/ RDREG read address or data register <br /> WAREG/ WDREG write address or data register <br /> RSREG read system control register <br /> WSREG write system control register <br /> READ read memory <br /> WRITE write memory <br /> DUMP read memory block <br /> FILL write memory block <br /> GO run CPU <br /> CALL call user patch code <br /> RST CPU reset instruction <br /> NOP null command <br />These commands closely mirror those that have been used for years in ROM mon <br />itors. <br />Single stepping is accomplished via hardware control of the BDM port or by p <br />lacing a <br />software breakpoint type of instruction in the code stream. <br />The processor is not aware of the BDM engine, it is not seen as an exception <br /> or interrupt. <br />There is a “background” instruction, “BGND” which causes the processor t <br />o enter BDM <br />when it is executed. BDM is left, and real- time code execution is resumed, <br />upon the GO <br />command being executed. <br /> <br />-- <br /> <br />※ 來源:·BBS 水木清華站 smth.org·[FROM: 202.117.114.7] <br /><a href="00000003.htm">上一篇</a><a href="javascript:history.go(-1)">返回上一頁</a><a href="index.htm">回到目錄</a><a href="#top">回到頁首</a><a href="00000005.htm">下一篇</a></h1></center><center><h1>BBS 水木清華站∶精華區</h1></center></body></html>
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