?? q7230.fit.talkback.xml
字號:
<!--
This XML file (created on Wed Jan 04 09:38:46 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>4.2</ver>
<schema>quartus_version_4.2_build_156.xsd</schema><license>
<host_id>000d567730b7</host_id>
<nic_id>000d567730b7</nic_id>
<cdrive_id>741bc671</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>4.2</version>
<build>Build 156</build>
<module>quartus_fit.exe</module>
<edition>Web Edition</edition>
<compilation_end_time>Wed Jan 04 09:38:46 2006</compilation_end_time>
</tool>
<machine>
<os>Windows 2000</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">2404</cpu_freq>
</cpu>
<ram units="MB">239</ram>
</machine>
<top_file>D:/PLD-Test/NEW/Q7230/Q7230</top_file>
<resource_usage_summary>
<rsc name="Logic cells" util="87" max=" 32 " type="int">28 </rsc>
<rsc name="Registers" util="31" max=" 32 " type="int">10 </rsc>
<rsc name="Number of pterms used" type="int">110</rsc>
<rsc name="User inserted logic elements" type="int">0</rsc>
<rsc name="I/O pins" util="67" max=" 34 " type="int">23 </rsc>
<rsc name="-- Clock pins" util="50" max=" 2 " type="int">1 </rsc>
<rsc name="-- Dedicated input pins" util="50" max=" 2 " type="int">1 </rsc>
<rsc name="Global signals" type="int">1</rsc>
<rsc name="Shareable expanders" util="50" max=" 32 " type="int">16 </rsc>
<rsc name="Parallel expanders" util="20" max=" 30 " type="int">6 </rsc>
<rsc name="Cells using turbo bit" util="87" max=" 32 " type="int">28 </rsc>
<rsc name="Maximum fan-out node" type="text">count[0]</rsc>
<rsc name="Maximum fan-out" type="int">19</rsc>
<rsc name="Total fan-out" type="int">268</rsc>
<rsc name="Average fan-out" type="float">4.00</rsc>
</resource_usage_summary>
<control_signals>
<row>
<name>CK~20</name>
<location>SEXP5</location>
<fan_out>1</fan_out>
<usage>Clock</usage>
<global>no</global>
</row>
<row>
<name>CLK</name>
<location>PIN_43</location>
<fan_out>9</fan_out>
<usage>Clock</usage>
<global>yes</global>
<global_resource_used>On</global_resource_used>
</row>
</control_signals>
<non_global_high_fan_out_signals>
<row>
<name>reduce_nor~16</name>
<fan_out>1</fan_out>
</row>
<row>
<name>reduce_nor~17</name>
<fan_out>2</fan_out>
</row>
<row>
<name>reduce_nor~18</name>
<fan_out>1</fan_out>
</row>
<row>
<name>reduce_nor~19</name>
<fan_out>1</fan_out>
</row>
<row>
<name>reduce_nor~25</name>
<fan_out>5</fan_out>
</row>
<row>
<name>reduce_nor~26</name>
<fan_out>1</fan_out>
</row>
<row>
<name>reduce_nor~27</name>
<fan_out>1</fan_out>
</row>
<row>
<name>reduce_nor~33</name>
<fan_out>6</fan_out>
</row>
<row>
<name>count[0]</name>
<fan_out>19</fan_out>
</row>
<row>
<name>rtl~560</name>
<fan_out>6</fan_out>
</row>
</non_global_high_fan_out_signals>
<interconnect_usage_summary>
<rsc name="Output enables" util="0" max=" 6 " type="int">0 </rsc>
<rsc name="PIA buffers" util="59" max=" 72 " type="int">43 </rsc>
</interconnect_usage_summary>
<mep_data>
<command_line>quartus_fit --import_settings_files=off --export_settings_files=off Q7230 -c Q7230</command_line>
</mep_data>
<software_data>
<speed_disk_usage_tradeoff>normal</speed_disk_usage_tradeoff>
</software_data>
<fitter_settings>
<row>
<option>Device</option>
<setting>EPM3032ALC44-10</setting>
</row>
<row>
<option>Use smart compilation</option>
<setting>Normal</setting>
<default_value>Normal</default_value>
</row>
<row>
<option>Optimize Timing</option>
<setting>Normal compilation</setting>
<default_value>Normal compilation</default_value>
</row>
<row>
<option>Optimize IOC Register Placement for Timing</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit to One Fitting Attempt</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Fitter Initial Placement Seed</option>
<setting>1</setting>
<default_value>1</default_value>
</row>
<row>
<option>Slow Slew Rate</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Fitter Effort</option>
<setting>Auto Fit</setting>
<default_value>Auto Fit</default_value>
</row>
</fitter_settings>
<fitter_device_options>
<row>
<option>Enable user-supplied start-up clock (CLKUSR)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide reset (DEV_CLRn)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide output enable (DEV_OE)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable INIT_DONE output</option>
<setting>Off</setting>
</row>
<row>
<option>Configuration scheme</option>
<setting>Passive Serial</setting>
</row>
<row>
<option>Reserve all unused pins</option>
<setting>As output driving an unspecified signal</setting>
</row>
<row>
<option>Security bit</option>
<setting>Off</setting>
</row>
<row>
<option>Base pin-out file on sameframe device</option>
<setting>Off</setting>
</row>
</fitter_device_options>
<input_pins>
<row>
<name>CLK</name>
<pin__>43</pin__>
<combinational_fan_out>9</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>yes</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>D</name>
<pin__>21</pin__>
<lab>1</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[0]</name>
<pin__>9</pin__>
<lab>1</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[1]</name>
<pin__>40</pin__>
<lab>2</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[2]</name>
<pin__>19</pin__>
<lab>1</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[3]</name>
<pin__>20</pin__>
<lab>1</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[4]</name>
<pin__>24</pin__>
<lab>2</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[5]</name>
<pin__>39</pin__>
<lab>2</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[6]</name>
<pin__>25</pin__>
<lab>2</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>Din[7]</name>
<pin__>18</pin__>
<lab>1</lab>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>G</name>
<pin__>33</pin__>
<lab>2</lab>
<combinational_fan_out>3</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>NAB</name>
<pin__>34</pin__>
<lab>2</lab>
<combinational_fan_out>2</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>OE</name>
<pin__>5</pin__>
<lab>1</lab>
<combinational_fan_out>9</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>clr</name>
<pin__>44</pin__>
<combinational_fan_out>11</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>reset</name>
<pin__>11</pin__>
<lab>1</lab>
<combinational_fan_out>18</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
</input_pins>
<output_pins>
<row>
<name>CK</name>
<pin__>6</pin__>
<lab>1</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>DQ</name>
<pin__>12</pin__>
<lab>1</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>NAA</name>
<pin__>16</pin__>
<lab>1</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>NDQ</name>
<pin__>41</pin__>
<lab>2</lab>
<output_register>no</output_register>
<slow_slew_rate>no</slow_slew_rate>
<open_drain>no</open_drain>
<tri_primitive>no</tri_primitive>
<i_o_standard>LVTTL</i_o_standard>
<location_assigned_by>Fitter</location_assigned_by>
</row>
</output_pins>
<compilation_summary>
<flow_status>Successful - Wed Jan 04 09:38:45 2006</flow_status>
<quartus_ii_version>4.2 Build 156 11/29/2004 SJ Web Edition</quartus_ii_version>
<revision_name>Q7230</revision_name>
<top_level_entity_name>TOP</top_level_entity_name>
<family>MAX3000A</family>
<device>EPM3032ALC44-10</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_macrocells>28 / 32 ( 87 % )</total_macrocells>
<total_pins>23 / 34 ( 67 % )</total_pins>
</compilation_summary>
<compile_id>43F63F46</compile_id>
<files>
<top>D:/PLD-Test/NEW/Q7230/TOP.vhd</top>
<extensions>
<ext ext_name="vwf">1</ext>
<ext ext_name="vhd">1</ext>
<ext ext_name="tdf">5</ext>
<ext ext_name="inc">8</ext>
<ext ext_name="lst">1</ext>
</extensions>
<sub_files>
<sub_file>D:/PLD-Test/NEW/Q7230/Q7230.vwf</sub_file>
<sub_file>D:/PLD-Test/NEW/Q7230/TOP.vhd</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/addcore.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/look_add.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/bypassff.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/altshift.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/aglobal42.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/cbx.lst</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/addcore.tdf</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/look_add.tdf</sub_file>
<sub_file>d:/comsof/altera/quartus42/libraries/megafunctions/altshift.tdf</sub_file>
</sub_files>
</files>
<architecture>
<family>MAX3000A</family>
<auto_device>OFF</auto_device>
<device>EPM3032ALC44-10</device>
</architecture>
<pkg_io>
<pin_std count="23">LVTTL</pin_std>
</pkg_io>
</talkback>
?? 快捷鍵說明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -