Analysis & Synthesis report for Q7230
Wed Jan 04 09:38:37 2006
Version 4.2 Build 156 11/29/2004 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Hierarchy
  5. User-Specified and Inferred Latches
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis Equations
  8. Analysis & Synthesis Source Files Read
  9. Analysis & Synthesis Resource Usage Summary
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary                                          ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jan 04 09:38:37 2006   ;
; Quartus II Version          ; 4.2 Build 156 11/29/2004 SJ Web Edition ;
; Revision Name               ; Q7230                                   ;
; Top-level Entity Name       ; TOP                                     ;
; Family                      ; MAX3000A                                ;
; Total macrocells            ; 28                                      ;
; Total pins                  ; 19                                      ;
+-----------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option                                                               ; Setting         ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device                                                               ; EPM3032ALC44-10 ;               ;
; Family name                                                          ; MAX3000A        ; Stratix       ;
; Top-level entity name                                                ; TOP             ; Q7230         ;
; Use smart compilation                                                ; Normal          ; Normal        ;
; Create Debugging Nodes for IP Cores                                  ; off             ; off           ;
; Preserve fewer node names                                            ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                            ; Off             ; Off           ;
; Verilog Version                                                      ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                         ; VHDL93          ; VHDL93        ;
; State Machine Processing                                             ; Auto            ; Auto          ;
; Extract Verilog State Machines                                       ; On              ; On            ;
; Extract VHDL State Machines                                          ; On              ; On            ;
; NOT Gate Push-Back                                                   ; On              ; On            ;
; Power-Up Don't Care                                                  ; On              ; On            ;
; Remove Redundant Logic Cells                                         ; Off             ; Off           ;
; Remove Duplicate Registers                                           ; On              ; On            ;
; Ignore CARRY Buffers                                                 ; Off             ; Off           ;
; Ignore CASCADE Buffers                                               ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                            ; Off             ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto            ; Auto          ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                       ; Off             ; Off           ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A         ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                                 ; On              ; On            ;
; Auto Logic Cell Insertion                                            ; On              ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4               ; 4             ;
; Auto Parallel Expanders                                              ; On              ; On            ;
; Auto Open-Drain Pins                                                 ; On              ; On            ;
; Remove Duplicate Logic                                               ; On              ; On            ;
; Auto Resource Sharing                                                ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A   ; 100             ; 100           ;
+----------------------------------------------------------------------+-----------------+---------------+


+-----------+
; Hierarchy ;
+-----------+
TOP
 |-- lpm_add_sub:add_rtl_0
      |-- addcore:adder
      |-- addcore:adder[0]
           |-- a_csnbuffer:cout_node
           |-- a_csnbuffer:oflow_node
           |-- a_csnbuffer:result_node
      |-- altshift:carry_ext_latency_ffs
      |-- look_add:look_ahead_unit
      |-- altshift:oflow_ext_latency_ffs
      |-- altshift:result_ext_latency_ffs
 |-- lpm_add_sub:add_rtl_1
      |-- addcore:adder
      |-- addcore:adder[0]
           |-- a_csnbuffer:cout_node
           |-- a_csnbuffer:oflow_node
           |-- a_csnbuffer:result_node
      |-- altshift:carry_ext_latency_ffs
      |-- look_add:look_ahead_unit
      |-- altshift:oflow_ext_latency_ffs