library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_bit.all;
entity TOP is 
 generic (Byte : integer := 8);
   port(
         CLK,OE,reset,G : in std_logic;
         D,clr  : in std_logic;
         NAB    : in std_logic;
         Din    : in std_logic_vector(Byte-1 downto 0);
         NAA    : out std_logic;
         CK     : buffer std_logic;
         DQ,NDQ : out std_logic
         
       );
end TOP;
----**********************************************------
architecture a of TOP is      
   signal  count :  std_logic_vector(Byte-1 downto 0) := (others=>'0');
   signal  Q :  std_logic_vector(Byte-1 downto 0) := (others=>'0');
   signal  CP_Q : std_logic :='0';
   signal  D_Q   : std_logic :='0';
 begin 
-------------------------------------------------------- 

  process (CLK,reset,G,clr)
   begin
    if reset= '1' then
      count<=(others=>'0');
     elsif CLK='1' and CLK'event then
      if clr='1' then
 
       if count=(Q-1) then          
        if G='0' then          -- Enable 74hc688
         count<=(others=>'0');
         CP_Q<=not CP_Q;
        else
         CP_Q<='0';
         end if;
       else                    -- UnEQU count ADD
         count<=count+1;
      end if;
    else
        count<=(others=>'0');
    end if;
    end if;
   CK<=not (NAB and CP_Q) after 10ns;
  end process;

 
---------------------------------------------------------
  Process (OE,reset)
    begin
      if reset='1' then
        Q<=(others=>'0');
      elsif OE='1' then
        Q<=Din;
      end if;   
  end Process;

---------------------------------------------------------
  
  Process(CK)
    begin
     if CK='1' and CK'event then
       D_Q<=D;
      else 
       D_Q<=D_Q;
    end if;
      
  end process;

----------------------------------------------------------
  
  NAA<= CP_Q;
  DQ<=D_Q;
  NDQ<=not D_Q;

end a;