?? fw.lst
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C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE FW
OBJECT MODULE PLACED IN fw.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE fw.c BROWSE DEBUG OBJECTEXTEND LISTINCLUDE SRC(.\fw.SRC)
stmt level source
1 //-----------------------------------------------------------------------------
2 // File: fw.c
3 // Contents: Firmware frameworks task dispatcher and device request parser
4 // source.
5 //
6 // indent 3. NO TABS!
7 //
8 // $Revision: 18 $
9 // $Date: 12/04/01 5:33p $
10 //
11 // Copyright (c) 1997 AnchorChips, Inc. All rights reserved
12 //-----------------------------------------------------------------------------
13 #include "fx2.h"
1 =1 //-----------------------------------------------------------------------------
2 =1 // File: FX2.h
3 =1 // Contents: EZ-USB FX2 constants, macros, datatypes, globals, and library
4 =1 // function prototypes.
5 =1 //
6 =1 // Copyright (c) 2000 Cypress Semiconductor, All rights reserved
7 =1 //-----------------------------------------------------------------------------
8 =1 #ifndef FX2_H //Header sentry
9 =1 #define FX2_H
10 =1
11 =1 #define INTERNAL_DSCR_ADDR 0x0080 // Relocate Descriptors to 0x80
12 =1 #define bmSTRETCH 0x07
13 =1 #define FW_STRETCH_VALUE 0x0 // Set stretch to 0 in frameworks
14 =1 // Note: a RevE eratta states that stretch must=0 to set OUTxBC
15 =1
16 =1 //-----------------------------------------------------------------------------
17 =1 // Constants
18 =1 //-----------------------------------------------------------------------------
19 =1 #define TRUE 1
20 =1 #define FALSE 0
21 =1
22 =1 #define bmBIT0 0x01
23 =1 #define bmBIT1 0x02
24 =1 #define bmBIT2 0x04
25 =1 #define bmBIT3 0x08
26 =1 #define bmBIT4 0x10
27 =1 #define bmBIT5 0x20
28 =1 #define bmBIT6 0x40
29 =1 #define bmBIT7 0x80
30 =1
31 =1 #define DEVICE_DSCR 0x01 // Descriptor type: Device
32 =1 #define CONFIG_DSCR 0x02 // Descriptor type: Configuration
33 =1 #define STRING_DSCR 0x03 // Descriptor type: String
34 =1 #define INTRFC_DSCR 0x04 // Descriptor type: Interface
35 =1 #define ENDPNT_DSCR 0x05 // Descriptor type: End Point
36 =1 #define DEVQUAL_DSCR 0x06 // Descriptor type: Device Qualifier
37 =1 #define OTHERSPEED_DSCR 0x07 // Descriptor type: Other Speed Configuration
38 =1
39 =1 #define bmBUSPWR bmBIT7 // Config. attribute: Bus powered
40 =1 #define bmSELFPWR bmBIT6 // Config. attribute: Self powered
41 =1 #define bmRWU bmBIT5 // Config. attribute: Remote Wakeup
42 =1
C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 2
43 =1 #define bmEPOUT bmBIT7
44 =1 #define bmEPIN 0x00
45 =1
46 =1 #define EP_CONTROL 0x00 // End Point type: Control
47 =1 #define EP_ISO 0x01 // End Point type: Isochronous
48 =1 #define EP_BULK 0x02 // End Point type: Bulk
49 =1 #define EP_INT 0x03 // End Point type: Interrupt
50 =1
51 =1 #define SUD_SIZE 8 // Setup data packet size
52 =1
53 =1 //////////////////////////////////////////////////////////////////////////////
54 =1 //Added for HID
55 =1
56 =1 #define SETUP_MASK 0x60 //Used to mask off request type
57 =1 #define SETUP_STANDARD_REQUEST 0 //Standard Request
58 =1 #define SETUP_CLASS_REQUEST 0x20 //Class Request
59 =1 #define SETUP_VENDOR_REQUEST 0x40 //Vendor Request
60 =1 #define SETUP_RESERVED_REQUEST 0x60 //Reserved or illegal request
61 =1
62 =1 //////////////////////////////////////////////////////////////////////////////
63 =1
64 =1
65 =1 #define SC_GET_STATUS 0x00 // Setup command: Get Status
66 =1 #define SC_CLEAR_FEATURE 0x01 // Setup command: Clear Feature
67 =1 #define SC_RESERVED 0x02 // Setup command: Reserved
68 =1 #define SC_SET_FEATURE 0x03 // Setup command: Set Feature
69 =1 #define SC_SET_ADDRESS 0x05 // Setup command: Set Address
70 =1 #define SC_GET_DESCRIPTOR 0x06 // Setup command: Get Descriptor
71 =1 #define SC_SET_DESCRIPTOR 0x07 // Setup command: Set Descriptor
72 =1 #define SC_GET_CONFIGURATION 0x08 // Setup command: Get Configuration
73 =1 #define SC_SET_CONFIGURATION 0x09 // Setup command: Set Configuration
74 =1 #define SC_GET_INTERFACE 0x0a // Setup command: Get Interface
75 =1 #define SC_SET_INTERFACE 0x0b // Setup command: Set Interface
76 =1 #define SC_SYNC_FRAME 0x0c // Setup command: Sync Frame
77 =1 #define SC_ANCHOR_LOAD 0xa0 // Setup command: Anchor load
78 =1
79 =1 #define GD_DEVICE 0x01 // Get descriptor: Device
80 =1 #define GD_CONFIGURATION 0x02 // Get descriptor: Configuration
81 =1 #define GD_STRING 0x03 // Get descriptor: String
82 =1 #define GD_INTERFACE 0x04 // Get descriptor: Interface
83 =1 #define GD_ENDPOINT 0x05 // Get descriptor: Endpoint
84 =1 #define GD_DEVICE_QUALIFIER 0x06 // Get descriptor: Device Qualifier
85 =1 #define GD_OTHER_SPEED_CONFIGURATION 0x07 // Get descriptor: Other Configuration
86 =1 #define GD_INTERFACE_POWER 0x08 // Get descriptor: Interface Power
87 =1 #define GD_HID 0x21 // Get descriptor: HID
88 =1 #define GD_REPORT 0x22 // Get descriptor: Report
89 =1
90 =1 #define GS_DEVICE 0x80 // Get Status: Device
91 =1 #define GS_INTERFACE 0x81 // Get Status: Interface
92 =1 #define GS_ENDPOINT 0x82 // Get Status: End Point
93 =1
94 =1 #define FT_DEVICE 0x00 // Feature: Device
95 =1 #define FT_ENDPOINT 0x02 // Feature: End Point
96 =1
97 =1 #define I2C_IDLE 0 // I2C Status: Idle mode
98 =1 #define I2C_SENDING 1 // I2C Status: I2C is sending data
99 =1 #define I2C_RECEIVING 2 // I2C Status: I2C is receiving data
100 =1 #define I2C_PRIME 3 // I2C Status: I2C is receiving the first byte of a string
101 =1 #define I2C_STOP 5 // I2C Status: I2C waiting for stop completion
102 =1 #define I2C_BERROR 6 // I2C Status: I2C error; Bit Error
103 =1 #define I2C_NACK 7 // I2C Status: I2C error; No Acknowledge
104 =1 #define I2C_OK 8 // I2C positive return code
C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 3
105 =1 #define I2C_WAITSTOP 9 // I2C Status: Wait for STOP complete
106 =1
107 =1 /*-----------------------------------------------------------------------------
108 =1 Macros
109 =1 -----------------------------------------------------------------------------*/
110 =1
111 =1 #define MSB(word) (BYTE)(((WORD)(word) >> 8) & 0xff)
112 =1 #define LSB(word) (BYTE)((WORD)(word) & 0xff)
113 =1
114 =1 #define SWAP_ENDIAN(word) ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1];\
115 =1 ((BYTE*)&word)[1] ^= ((BYTE*)&word)[0];\
116 =1 ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]
117 =1
118 =1 #define EZUSB_IRQ_ENABLE() EUSB = 1
119 =1 #define EZUSB_IRQ_DISABLE() EUSB = 0
120 =1 #define EZUSB_IRQ_CLEAR() EXIF &= ~0x10 // IE2_
121 =1
122 =1 #define EZUSB_STALL_EP0() EP0CS |= bmEPSTALL
123 =1 #define EZUSB_STALL_EP(ep_id) // fx2bug
124 =1 #define EZUSB_UNSTALL_EP(ep_id) // fx2bug
125 =1 #define EZUSB_GET_EP_STATUS(ep_id) // fx2bug
126 =1 #define EZUSB_SET_EP_BYTES(ep_id,count) // fx2bug
127 =1
128 =1
129 =1 // WRITEDELAY() has been replaced by SYNCDELAY; macro in fx2sdly.h
130 =1 // ...it is here for backwards compatibility...
131 =1
132 =1 // the WRITEDELAY macro compiles to the time equivalent of 3 NOPs.
133 =1 // It is used in the frameworks to allow for write recovery time
134 =1 // requirements of certain registers. This is only necessary for
135 =1 // EZ-USB FX parts. See the EZ-USB FX TRM for
136 =1 // more information on write recovery time issues.
137 =1 #define WRITEDELAY() {char writedelaydummy = 0;}
138 =1 // if this firmware will never run on an EZ-USB FX part replace
139 =1 // with:
140 =1 // #define WRITEDELAY()
141 =1
142 =1 // macro to reset and endpoint data toggle
143 =1 #define EZUSB_RESET_DATA_TOGGLE(ep) TOGCTL = (((ep & 0x80) >> 3) + (ep & 0x0F));\
144 =1 TOGCTL |= bmRESETTOGGLE
145 =1
146 =1
147 =1 #define EZUSB_ENABLE_RSMIRQ() (EICON |= 0x20) // Enable Resume Interrupt (EPFI_)
148 =1 #define EZUSB_DISABLE_RSMIRQ() (EICON &= ~0x20) // Disable Resume Interrupt (EPFI_)
149 =1 #define EZUSB_CLEAR_RSMIRQ() (EICON &= ~0x10) // Clear Resume Interrupt Flag (PFI_)
150 =1
151 =1 #define EZUSB_GETI2CSTATUS() (I2CPckt.status)
152 =1 #define EZUSB_CLEARI2CSTATUS() if((I2CPckt.status == I2C_BERROR) || (I2CPckt.status == I2C_NACK))\
153 =1 I2CPckt.status = I2C_IDLE;
154 =1
155 =1 #define EZUSB_ENABLEBP() (BREAKPT |= bmBPEN) // TGE fx2bug
156 =1 #define EZUSB_DISABLEBP() (BREAKPT &= ~bmBPEN) // TGE fx2bug
157 =1 #define EZUSB_CLEARBP() (BREAKPT |= bmBREAK) // TGE fx2bug
158 =1 #define EZUSB_BP(addr) BPADDRH = (BYTE)(((WORD)addr >> 8) & 0xff);\
159 =1 BPADDRL = (BYTE)addr // TGE fx2bug
160 =1
161 =1 #define EZUSB_EXTWAKEUP() (((WAKEUPCS & bmWU2) && (WAKEUPCS & bmWU2EN)) ||\
162 =1 ((WAKEUPCS & bmWU) && (WAKEUPCS & bmWUEN)))
163 =1
164 =1 #define EZUSB_HIGHSPEED() (USBCS & bmHSM)
165 =1
166 =1 //-----------------------------------------------------------------------------
C51 COMPILER V7.06 FW 12/29/2005 11:19:53 PAGE 4
167 =1 // Datatypes
168 =1 //-----------------------------------------------------------------------------
169 =1 typedef unsigned char BYTE;
170 =1 typedef unsigned short WORD;
171 =1 typedef unsigned long DWORD;
172 =1 typedef bit BOOL;
173 =1
174 =1 #define INT0_VECT 0
175 =1 #define TMR0_VECT 1
176 =1 #define INT1_VECT 2
177 =1 #define TMR1_VECT 3
178 =1 #define COM0_VECT 4
179 =1 #define TMR2_VECT 5
180 =1 #define WKUP_VECT 6
181 =1 #define COM1_VECT 7
182 =1 #define USB_VECT 8
183 =1 #define I2C_VECT 9
184 =1 #define INT4_VECT 10
185 =1 #define INT5_VECT 11
186 =1 #define INT6_VECT 12
187 =1
188 =1
189 =1 // TGE fx2bug
190 =1 #define SUDAV_USBVECT (0 << 2)
191 =1 #define SOF_USBVECT (1 << 2)
192 =1 #define SUTOK_USBVECT (2 << 2)
193 =1 #define SUSP_USBVECT (3 << 2)
194 =1 #define URES_USBVECT (4 << 2)
195 =1 #define HS_USBVECT (5 << 2)
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