?? bulkloop.c
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#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File: bulkloop.c
// Contents: Hooks required to implement USB peripheral function.
//
// Copyright (c) 2000 Cypress Semiconductor All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
BYTE Highspeed;
WORD xfrcnt = 64;
sbit RDCLKA = IOA ^ 6;
#define VR_NAKALL_ON 0xD0 //制造商請求
#define VR_NAKALL_OFF 0xD1
#define SINGLEWRITE 0xB0
#define SINGLEREAD 0xB1
#define SPEED 0xB2
WORD j;
BYTE rddr;
BYTE AD;
BYTE D16;
WORD i;
void rddata(BYTE AD);
void rddata16(BYTE AD);
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
// CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;
CPUCS = 0x30;
SYNCDELAY;
// set the slave FIFO interface to 48MHz
// IFCONFIG |= 0x40;
//OEB|=0xFF //
// Registers which require a synchronization delay, see section 15.14
// FIFORESET FIFOPINPOLAR
// INPKTEND OUTPKTEND
// EPxBCH:L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH:L EPxAUTOINLENH:L
// EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH:L
// UDMACRCH:L EPxGPIFTRIG
// GPIFTRIG
// Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
// ...these have been replaced by GPIFTC[B3:B0] registers
// default: all endpoints have their VALID bit set
// default: TYPE1 = 1 and TYPE0 = 0 --> BULK
// default: EP2 and EP4 DIR bits are 0 (OUT direction)
// default: EP6 and EP8 DIR bits are 1 (IN direction)
// default: EP2, EP4, EP6, and EP8 are double buffered
// we are just using the default values, yes this is not necessary...
EP1OUTCFG = 0xA0;
SYNCDELAY;
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0xA2;
SYNCDELAY;
EP4CFG = 0xA0;
SYNCDELAY;
EP6CFG = 0xE2;
SYNCDELAY;
EP8CFG = 0xE0;
// out endpoints do not come up armed
// since the defaults are double buffered we must write dummy byte counts twice
SYNCDELAY;
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY;
EP2BCL = 0x80;
SYNCDELAY;
EP4BCL = 0x80; // arm EP4OUT by writing byte count w/skip.
SYNCDELAY;
EP4BCL = 0x80;
// enable dual autopointer feature
AUTOPTRSETUP |= 0x01;
SYNCDELAY;
PORTACFG = 0x00;
OEB |= 0xFF;
OEA |= 0xFF;
OEE |= 0XFF;
Rwuen = TRUE; // Enable remote-wakeup
// EPIE=0x10;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
if(!(EP2468STAT & bmEP2EMPTY))
{ // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
IOB= EP2FIFOBUF[0]; //addr output
D16= EP2FIFOBUF[1]; //D16 OR D8
OEC=0x00; //C inport
AD=EP2FIFOBUF[0];
switch(D16)
{
case 0x00: //D8
rddata(AD);
break;
case 0xFF:
rddata16(AD);
break;
default: //D16
rddata(AD);
}
EP2BCL = 0x80;
}
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
AlternateSetting = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
{
return(TRUE);
}
BOOL DR_ClearFeature(void)
{
return(TRUE);
}
BOOL DR_SetFeature(void)
{
return(TRUE);
}
BOOL DR_VendorCmnd(void)
{
BYTE tmp;
switch (SETUPDAT[1])
{
case VR_NAKALL_ON:
tmp = FIFORESET;
tmp |= bmNAKALL;
SYNCDELAY;
FIFORESET = tmp;
break;
case VR_NAKALL_OFF:
tmp = FIFORESET;
tmp &= ~bmNAKALL;
SYNCDELAY;
FIFORESET = tmp;
break;
case SINGLEWRITE: //single write,data in SETUPDAT[2],ram address in SETUPDAT[4]
OEC |= 0xFF;
IOB = SETUPDAT[4];
tmp = SETUPDAT[2];
IOC = tmp;
SYNCDELAY;
SYNCDELAY;
//IOA=0x00;
IOB=0x36;
OEC=0x00;
EP0BUF[1]=IOC;
EP0BUF[0] = SETUPDAT[4]; //隨便返回一個值,用于測試
//EP0BUF[5] = tmp;
EP0BCH = 0; //這兩句保留
EP0BCL = 8;
break;
case SINGLEREAD: //single read,ram address in SETUPDAT[4],put the data in EP0BUF[0]
OEC &= 0x00;
IOB = SETUPDAT[4];
EP0BUF[0] = IOC;
EP0BCH = 0; //這兩句保留
EP0BCL = 8;
break;
case SPEED:
if(Highspeed==1)
{
xfrcnt = 512;
}
else xfrcnt = 64;
EP0BUF[0] = Highspeed;
EP0BUF[1] = xfrcnt>>8;
EP0BUF[2] = (BYTE)xfrcnt;
EP0BCH = 0;
EP0BCL = 8;
break;
default:
return(TRUE);
}
return(FALSE);
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures(void) interrupt 0
{
// whenever we get a USB reset, we should revert to full speed mode
pConfigDscr = pFullSpeedConfigDscr;
((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
pOtherConfigDscr = pHighSpeedConfigDscr;
((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
Highspeed = 0;
EZUSB_IRQ_CLEAR();
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp(void) interrupt 0
{
Sleep = TRUE;
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