EZUSB_IRQ_CLEAR();
   USBIRQ = bmSUSP;
}

void ISR_Highspeed(void) interrupt 0
{
   if (EZUSB_HIGHSPEED())
   {
      pConfigDscr = pHighSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
      pOtherConfigDscr = pFullSpeedConfigDscr;
      ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
   }

   EZUSB_IRQ_CLEAR();
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
/*
   if(!(EP2468STAT & bmEP2EMPTY))
    { // check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
     //EP2FIFOBUF[1] = ~EP2FIFOBUF[0];
//jj=0x00;
//EP2FIFOBUF[0]=jj;
      //IOB= EP2FIFOBUF[0];   //addr output
	  AD=EP2FIFOBUF[0];
      j=0x40&EP2FIFOBUF[0];
	  switch(j)
	  {
	   case 0x00:          //master channel
	      rddr=0x04;
          rddata(rddr,AD);  
    	  break;
	   default:            //slave channel 
	      rddr=0x44;
	      rddata(rddr,AD);  
 
	  }
/*   if(EP2FIFOBUF[0]==0x00)
      IOD= EP2FIFOBUF[1];
        
  else
     {
      IOB= EP2FIFOBUF[0];   //addr output
	   j=EP2FIFOBUF[0];
      switch (j){
         case 0x0f:           
              sw=0x00;
              in6(sw);
			  break;
         case 0x8f:
              sw=0x01;
              in6(sw);
			  break;
         case 0xcf:
              sw=0x02;
              in6(sw);
			  break;
         case 0xef:                
              sw=0x03;             
              in6(sw);             
              break;               
         case 0xf7:                
              sw=0x04;             
              in6(sw);             
              break;               
         case 0xfb:                
              sw=0x05;             
              in6(sw);             
              break;               
         case 0xfd:
              sw= 0x06;
              in6(sw);                         
              break;                     
         case 0xfe:
              sw=0x07;
              in6(sw);
              break;
         default:
              sw=0x00;
              in6(sw);   
            }
          }
   EP2BCL = 0x80;
  
     //IOB = ~EP2FIFOBUF[0];
     // if(!(EP2468STAT & bmEP6FULL))
     //  {  // check EP6 FULL(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is full
     //   APTR1H = MSB( &EP2FIFOBUF );
     //   APTR1L = LSB( &EP2FIFOBUF );

     //   AUTOPTRH2 = MSB( &EP6FIFOBUF );
     //   AUTOPTRL2 = LSB( &EP6FIFOBUF );

     //   count = (EP2BCH << 8) + EP2BCL;

     //   // loop EP2OUT buffer data to EP6IN
     //   for( i = 0x0000; i < count; i++ )
     //   {
     //      // setup to transfer EP2OUT buffer to EP6IN buffer using AUTOPOINTER(s)
     //      EXTAUTODAT2 = EXTAUTODAT1;
     //   }
     //   EP6BCH = EP2BCH;  
     //   SYNCDELAY;  
     //   EP6BCL = EP2BCL;        // arm EP6IN
     //   SYNCDELAY;                    
     //   EP2BCL = 0x80;          // re(arm) EP2OUT
   //  }
     // SYNCDELAY;
       
    }
   EZUSB_IRQ_CLEAR();
   EPIRQ = 0x10;   
*/
 }
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{ 
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}
/*
void rddata(BYTE rddr,BYTE AD)
{
if(!(EP2468STAT & bmEP6FULL))
  {
      for(i=0;i<64;i++)
	    {
        IOB=rddr;       //M&S channel rd_clk addr
		 SYNCDELAY;
		 SYNCDELAY;
		 SYNCDELAY;
		 SYNCDELAY;
		 OEC=0xFF;     //C outport
		 SYNCDELAY;
		 SYNCDELAY;
		 RDCLK=0;        //set_clk=0
		 SYNCDELAY;
		 SYNCDELAY;
		 OEC=0x00;   //C inport
		 SYNCDELAY;
		 SYNCDELAY;
		 IOB=AD;
		 SYNCDELAY;
		 SYNCDELAY;
		 EP6FIFOBUF[i]=IOC;
		 SYNCDELAY;
		 SYNCDELAY;
		 RDCLK=1;        //set_clk=1
		 
		}
   	EP6BCH = 0;	
	EP6BCL = 0x40;
  }

}

/*
void in6(WORD sw)

{  if(!(EP2468STAT & bmEP6FULL))

      {
         IOA=sw;
         SYNCDELAY;
         
         SYNCDELAY;
         SYNCDELAY; 
         SYNCDELAY;
	    EP6FIFOBUF[0] = IOC;    
	   // EP6FIFOBUF[0] = CPUCS;
	    EP6BCH = 0;             
	    SYNCDELAY;
         SYNCDELAY;     
	    EP6BCL = 1;             
	                            
       }        

}

*/