BSP             .set    0   ; 5409 DSK audio in/out codec uses McBSP0
SAMPLERATE      .set  8

    
    .mmregs
SPCR1_VAL       .set    0000h

SPCR2_VAL       .set    0200h

RCR1_VAL        .set    040h

RCR2_VAL        .set    004h

XCR1_VAL        .set    040h

XCR2_VAL        .set    004h
PCR_VAL .set    0Ch


MCBSP0_TO_CODEC0 .set 0xFE
MCBSP1_TO_CODEC1 .set 0xFD
CODEC1_FC_ON    .set 0x8
CODEC0_FC_ON    .set 0x4
CPLD_CTRL2      .set 0x4

* McBSP Memory Mapped Registers
SPSA0           .set    038h
SPSD0           .set    039h
DRR10           .set    021h
DXR10           .set    023h
SPSA1           .set    048h
SPSD1           .set    049h
DRR11           .set    041h
DXR11           .set    043h

* McBSP Subaddresed Registers
SPCR1           .set    00h
SPCR2           .set    01h
RCR1            .set    02h
RCR2            .set    03h
XCR1            .set    04h
XCR2            .set    05h
SRGR1           .set    06h
SRGR2           .set    07h
PCR             .set    0Eh

;; Choose appropriate sub-address registers and DRR/DXR

        .if BSP = 0
SPSA    .set SPSA0
SPSD    .set SPSD0
RDRR    .set    21H            ; McBSP0 data receive register 1
RDXR    .set    23H           ; McBSP0 data transmit register 1
MCBSP_TO_CODEC .set MCBSP0_TO_CODEC0
IMASK   .set  (1 << 4)
        .endif

WR_MCBSP_SUB_REG        .macro  addr,val
                        stm     addr,SPSA
                        nop
                        stm     val,SPSD
                        nop
                        .endm

RD_MCBSP_SUB_REG        .macro  addr,acc
                        stm     #:addr:,SPSA
                        nop
                        ldm     SPSD,acc
                        nop
                        nop
                        nop
                        .endm

WAITTRX   .macro             ; Wait for serial port to Rx word
WAITR?
        RD_MCBSP_SUB_REG        SPCR1,A
        and #1<<1, A
        bc   WAITR?, AEQ
          .endm

PROGREG   .macro    progword
     
 		stm  #01h,RDXR       
        WAITTRX
        stm     #:progword:,RDXR
        WAITTRX
          .endm               

wait   .macro
  		STM #0008h, AR0 ;AR0 points to ACCL
		RPT *AR0 		;repeat the # of times specified in ACCL
		NOP 			;do nothing in the delay loop
		.endm 			


    .global RESET,AIC_INIT,WAIT_INT,_CPU_to_codec_ch1,READ_SAMPLES
     .text
     .mmregs
     .def _main


p0_serialflag  .set 060h
p0_serialint   .set 061h

SYSTEM_STACK   .set 04000h

          .text
_main
     ld   #0, DP              
     ssbx INTM      
     ssbx SXM  
     st   #0, p0_serialint
     st   #2491h, SWWSR  ;2 wait except for on-chip data
     st   #0ffe0h, PMST  ; MP/MC = 1, IPTR = 1ff  
     st #0f007h,clkmd
     st   #1, p0_serialflag


;*************************************************************************
;*   audio_init:
;*************************************************************************
_DSS_init
     rsbx CPL
     nop                 ; cpl latency
     nop                 ; cpl latency
     nop                 ; cpl latency

     ld   #0, DP              
     ssbx INTM      
     ssbx SXM  

     WR_MCBSP_SUB_REG   SPCR1,	#SPCR1_VAL
     WR_MCBSP_SUB_REG   SPCR2,	#SPCR2_VAL

     WR_MCBSP_SUB_REG   PCR,	#PCR_VAL
     
     WR_MCBSP_SUB_REG   SPCR1,	#0h               ; reset McBSP0
     WR_MCBSP_SUB_REG   SPCR2,	#0h

     ;; write McBSP registers        
     WR_MCBSP_SUB_REG   RCR1,	#RCR1_VAL
     WR_MCBSP_SUB_REG   RCR2,	#RCR2_VAL
        
     WR_MCBSP_SUB_REG   XCR1,	#XCR1_VAL
     WR_MCBSP_SUB_REG   XCR2,	#XCR2_VAL
        
		LD #100 ,A        
    	WAIT

     ;; set interrupts to come from serial ports not DMA
     ;; by clearing bits 6 and 7 in DMPREC
     andm       #0ff3fh, 54h

 
     ;; clear xmit register -- why?
     stm 	#0, RDXR

     ;; now enable McBSP transmit and receive
     WR_MCBSP_SUB_REG   SPCR1,#SPCR1_VAL | 1
     WR_MCBSP_SUB_REG   SPCR2,#SPCR2_VAL | 1
     	LD #100 ,A        
     WAIT

_AIC_INIT    
	 STM  #0,		IMR
     orm  #IMASK, 	IMR          ;only receive-int is served.
   ;  orm  #08h, 	IMR
   
     stm  #0ffffh, 	IFR                  
     
;    PROGREG 0000010100001000b
     PROGREG 0000001100000001b
             ;      876543210
     PROGREG 0000010000010000b
             ;      876543210

     ld   RDRR, A
     ld   RDRR, A

     stlm A,RDXR
     stlm A,RDXR
   
    rsbx INTM
     nop                 ; cpl latency
     nop                 ; cpl latency
     nop                 ; cpl latency
     
_js           
    	
;   	 idle 1
	nop
	nop
	nop
	nop
	nop
			
	b _js     

_CPU_to_codec_ch1
     st   #1, p0_serialint    ;controlling AIC init, not used later

	LDM  	RDRR,	a
	STL 	A,	RDXR

	rete
     
     

    .if __far_mode
        fret
    .else
        ret
    .endif
 

    .end