?? canary.h
字號(hào):
/*H***************************************************************************
* NAME: 89C51CC01.h
*----------------------------------------------------------------------------
* PURPOSE:
*****************************************************************************/
#include "compiler.h"
#ifndef _89C51CC01_H_
#define _89C51CC01_H_
/*----------------------------------------*/
/* Include file for 8051 SFR Definitions */
/*----------------------------------------*/
/* BYTE Register */
Sfr (P0 , 0x80);
Sfr (P1 , 0x90);
Sbit (P1_7 , P1, 7);
Sbit (P1_6 , P1, 6);
Sbit (P1_5 , P1, 5);
Sbit (P1_4 , P1, 4);
Sbit (P1_3 , P1, 3);
Sbit (P1_2 , P1, 2);
Sbit (P1_1 , P1, 1);
Sbit (P1_0 , P1, 0);
Sfr (P2 , 0xA0);
Sfr (P3 , 0xB0);
Sbit (P3_7 , P3, 7);
Sbit (P3_6 , P3, 6);
Sbit (P3_5 , P3, 5);
Sbit (P3_4 , P3, 4);
Sbit (P3_3 , P3, 3);
Sbit (P3_2 , P3, 2);
Sbit (P3_1 , P3, 1);
Sbit (P3_0 , P3, 0);
Sbit (RD , P3, 7);
Sbit (WR , P3, 6);
Sbit (T1 , P3, 5);
Sbit (T0 , P3, 4);
Sbit (INT1 , P3, 3);
Sbit (INT0 , P3, 2);
Sbit (TXD , P3, 1);
Sbit (RXD , P3, 0);
Sfr (P4 , 0xC0);
Sfr (PSW , 0xD0);
Sbit (CY , PSW , 7);
Sbit (AC , PSW , 6);
Sbit (F0 , PSW , 5);
Sbit (RS1 , PSW , 4);
Sbit (RS0 , PSW , 3);
Sbit (OV , PSW , 2);
Sbit (UD , PSW , 1);
Sbit (P , PSW , 0);
Sfr (ACC , 0xE0);
Sfr (B , 0xF0);
Sfr (SP , 0x81);
Sfr16 (DPTR, 0x82);
Sfr (DPL , 0x82);
Sfr (DPH , 0x83);
Sfr (PCON , 0x87);
Sfr (CKCON , 0x8F);
/*------------------ TIMERS registers ---------------------*/
Sfr (TCON , 0x88);
Sbit (TF1 , TCON, 7);
Sbit (TR1 , TCON, 6);
Sbit (TF0 , TCON, 5);
Sbit (TR0 , TCON, 4);
Sbit (IT1 , TCON, 2);
Sbit (IT0 , TCON, 0);
Sfr (TMOD , 0x89);
Sfr (T2CON , 0xC8);
Sbit (TF2 , T2CON, 7);
Sbit (EXF2 , T2CON, 6);
Sbit (RCLK , T2CON, 5);
Sbit (TCLK , T2CON, 4);
Sbit (EXEN2 , T2CON, 3);
Sbit (TR2 , T2CON, 2);
Sbit (C_T2 , T2CON, 1);
Sbit (CP_RL2, T2CON, 0);
Sfr (T2MOD , 0xC9);
Sfr (TL0 , 0x8A);
Sfr (TL1 , 0x8B);
Sfr (TL2 , 0xCC);
Sfr (TH0 , 0x8C);
Sfr (TH1 , 0x8D);
Sfr (TH2 , 0xCD);
Sfr (RCAP2L , 0xCA);
Sfr (RCAP2H , 0xCB);
Sfr (WDTRST , 0xA6);
Sfr (WDTPRG , 0xA7);
/*------------------- UART registers ------------------------*/
Sfr (SCON , 0x98);
Sbit (SM0 , SCON, 7);
Sbit (FE , SCON, 7);
Sbit (SM1 , SCON, 6);
Sbit (SM2 , SCON, 5);
Sbit (REN , SCON, 4);
Sbit (TB8 , SCON, 3);
Sbit (RB8 , SCON, 2);
Sbit (TI , SCON, 1);
Sbit (RI , SCON, 0);
Sfr (SBUF , 0x99);
Sfr (SADEN , 0xB9);
Sfr (SADDR , 0xA9);
/*-------------------- ADC registers ----------------------*/
Sfr (ADCLK , 0xF2);
Sfr (ADCON , 0xF3);
#define MSK_ADCON_PSIDLE 0x40
#define MSK_ADCON_ADEN 0x20
#define MSK_ADCON_ADEOC 0x10
#define MSK_ADCON_ADSST 0x08
#define MSK_ADCON_SCH 0x07
Sfr (ADDL , 0xF4);
#define MSK_ADDL_UTILS 0x03
Sfr (ADDH , 0xF5);
Sfr (ADCF , 0xF6);
/*-------------------- FLASH EEPROM registers ------------*/
Sfr (FPGACON , 0xF1);
#define MSK_FPGACON_FM2ACCESS 0x01
Sfr (FCON , 0xD1);
#define MSK_FCON_FBUSY 0x01
#define MSK_FCON_FMOD 0x06
#define MSK_FCON_FPS 0x08
#define MSK_FCON_FPL 0xF0
Sfr (EECON , 0xD2);
#define MSK_EECON_EEBUSY 0x01
#define MSK_EECON_EEE 0x02
#define MSK_EECON_EEPL 0xF0
Sfr (AUXR , 0x8E);
#define MSK_AUXR_M0 0x20
Sfr (AUXR1 , 0xA2);
/*-------------------- IT registers -----------------------*/
Sfr (IPL1 , 0xF8);
Sfr (IPH1 , 0xF7);
Sfr (IE0 , 0xA8);
Sfr (IPL0 , 0xB8);
Sfr (IPH0 , 0xB7);
Sfr (IE1 , 0xE8);
/* IE0 */
Sbit (EA , IE0, 7);
Sbit (EC , IE0, 6);
Sbit (ET2 , IE0, 5);
Sbit (ES , IE0, 4);
Sbit (ET1 , IE0, 3);
Sbit (EX1 , IE0, 2);
Sbit (ET0 , IE0, 1);
Sbit (EX0 , IE0, 0);
/* IE1 */
Sbit (ETIM , IE1, 2);
Sbit (EADC , IE1, 1);
Sbit (ECAN , IE1, 0);
/*--------------------- PCA registers --------------------*/
Sfr (CCON , 0xD8);
Sfr (CMOD , 0xD9);
Sfr (CH , 0xF9);
Sfr (CL , 0xE9);
Sfr (CCAP0H , 0xFA);
Sfr (CCAP0L , 0xEA);
Sfr (CCAPM0 , 0xDA);
Sfr (CCAP1H , 0xFB);
Sfr (CCAP1L , 0xEB);
Sfr (CCAPM1 , 0xDB);
Sfr (CCAP2H , 0xFC);
Sfr (CCAP2L , 0xEC);
Sfr (CCAPM2 , 0xDC);
Sfr (CCAP3H , 0xFD);
Sfr (CCAP3L , 0xED);
Sfr (CCAPM3 , 0xDD);
Sfr (CCAP4H , 0xFE);
Sfr (CCAP4L , 0xEE);
Sfr (CCAPM4 , 0xDE);
/*------------------- CAN registers --------------------------*/
#ifndef OLD_SFR
Sfr (CANGIT , 0x9B);
#define MSK_CANGIT_CANIT 0x80
#define MSK_CANGIT_OVRTIM 0x20
#define MSK_CANGIT_OVRBUF 0x10
#define MSK_CANGIT_SERG 0x08
#define MSK_CANGIT_CERG 0x04
#define MSK_CANGIT_FERG 0x02
#define MSK_CANGIT_AERG 0x01
#endif /* OLD_SFR */
Sfr (CANTEC , 0x9C);
Sfr (CANREC , 0x9D);
Sfr (CANTCON , 0xA1);
Sfr (CANMSG , 0xA3);
Sfr (CANTTCL , 0xA4);
Sfr (CANTTCH , 0xA5);
Sfr (CANGSTA , 0xAA);
#ifdef OLD_SFR
#define MSK_CANGSTA_OVRTIM 0x20
#endif
#ifndef OLD_SFR
#define MSK_CANGSTA_OVFG 0x40
#define MSK_CANGSTA_TBSY 0x10
#define MSK_CANGSTA_RBSY 0x08
#define MSK_CANGSTA_ENFG 0x04
#define MSK_CANGSTA_BOFF 0x02
#define MSK_CANGSTA_ERRP 0x01
#endif /* OLD_SFR */
Sfr (CANGCON , 0xAB);
#define MSK_CANGCON_ABRQ 0x80
#define MSK_CANGCON_OVRQ 0x40
#define MSK_CANGCON_TTC 0x20
#define MSK_CANGCON_SYNCTTC 0x10
#define TTC_EOF 0x10
#define TTC_SOF 0x00
#define MSK_CANGCON_AUTBAUD 0x08
#define MSK_CANGCON_ENA 0x02
#define MSK_CANGCON_GRES 0x01
Sfr (CANTIML , 0xAC);
Sfr (CANTIMH , 0xAD);
Sfr (CANSTMPL , 0xAE);
Sfr (CANSTMPH , 0xAF);
Sfr (CANPAGE , 0xB1);
Sfr (CANSTCH , 0xB2);
#define MSK_CANSTCH_DLCW 0x80
#define MSK_CANSTCH_TxOk 0x40
#define MSK_CANSTCH_RxOk 0x20
#define MSK_CANSTCH_BERR 0x10
#define MSK_CANSTCH_SERR 0x08
#define MSK_CANSTCH_CERR 0x04
#define MSK_CANSTCH_FERR 0x02
#define MSK_CANSTCH_AERR 0x01
Sfr (CANCONCH , 0xB3);
#define MSK_CANCONCH_IDE 0x10
#define MSK_CANCONCH_DLC 0x0F
#define MSK_CANCONCH_CONF 0xC0
#define DLC_MAX 8
#define CH_DISABLE 0x00
#define CH_RxENA 0x80
#define CH_TxENA 0x40
#define CH_RxBENA 0xC0
Sfr (CANBT1 , 0xB4);
#define CAN_PRESCALER_MIN 0
#define CAN_PRESCALER_MAX 63
Sfr (CANBT2 , 0xB5);
#define MSK_CANBT2_SJW 0x60
#define MSK_CANBT2_PRS 0x0E
#define CAN_SJW_MIN 0
#define CAN_SJW_MAX 3
#define CAN_PRS_MIN 0
#define CAN_PRS_MAX 7
Sfr (CANBT3 , 0xB6);
#define MSK_CANBT3_PHS2 0x70
#define MSK_CANBT3_PHS1 0x0E
#define CAN_PHS2_MIN 0
#define CAN_PHS2_MAX 7
#define CAN_PHS1_MIN 0
#define CAN_PHS1_MAX 7
Sfr (CANSIT1 , 0xBA);
#ifdef OLD_SRF
#define MSK_CANSIT1_OVRBUF 0x80
#endif /* OLD_SFR */
Sfr (CANSIT2 , 0xBB);
Sfr (CANIDT1 , 0xBC);
Sfr (CANIDT2 , 0xBD);
Sfr (CANIDT3 , 0xBE);
Sfr (CANIDT4 , 0xBF);
#define MSK_CANIDT4_RTRTAG 0x04
Sfr (CANGIE , 0xC1);
#ifndef OLD_SFR
#define MSK_CANGIE_ENRX 0x20
#define MSK_CANGIE_ENTX 0x10
#define MSK_CANGIE_ENERCH 0x08
#define MSK_CANGIE_ENBUF 0x04
#define MSK_CANGIE_ENERG 0x02
#endif
#ifdef OLD_SFR
#define MSK_CANGIE_ENRX 0x20
#define MSK_CANGIE_ENTX 0x10
#define MSK_CANGIE_ENER 0x08
#define MSK_CANGIE_ENBUF 0x04
#endif /* OLd_SFR */
Sfr (CANIE1 , 0xC2);
Sfr (CANIE2 , 0xC3);
Sfr (CANIDM1 , 0xC4);
Sfr (CANIDM2 , 0xC5);
Sfr (CANIDM3 , 0xC6);
Sfr (CANIDM4 , 0xC7);
#define MSK_CANIDM4_RTRMSK 0x04
#define MSK_CANIDM4_IDEMSK 0x01
Sfr (CANEN1 , 0xCE);
Sfr (CANEN2 , 0xCF);
#endif
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