.module do_RLR4;
.external tmp;
.entry RLR4;

RLR4:
        i0=^tmp+3;
        i1=^tmp+2;
        i2=i0;
        m0=4;
                                
        si=dm(i0,m0);
        ay0=dm(i1,m0);
        
        cntr=3;
        do rlrx4 until ce;
                sr=ashift si (hi),      si=dm(i0,m0);
                ar=sr1-ay0,             ay0=dm(i1,m0);
        rlrx4:  dm(i2,m0)=ar;
   
        sr=ashift si (hi);
        ar=sr1-ay0;
                             dm(i2,m0)=ar;
        rts;
.endmod;