.module do_RLR4_8;
.external tmp;
.entry RLR4_8;

RLR4_8:
        i0=^tmp+3;
        i1=^tmp+2;
        i2=i0;
        m0=4;
                                si=dm(i0,m0);
                                ay0=dm(i1,m0);
        sr=ashift si (hi),      si=dm(i0,m0);
        ar=sr1-ay0,             ay0=dm(i1,m0);
                        dm(i2,m0)=ar;
        sr=ashift si (hi);
        ar=sr1-ay0;
                        dm(i2,m0)=ar;
        rts;
.endmod;