if (!to)		printk(KERN_WARNING "HiSax: waitforXFW timeout\n");}static inline voidMemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u_char data){	long flags;	save_flags(flags);	cli();	MemwaitforCEC(cs, hscx);	MemWriteHSCX(cs, hscx, HSCX_CMDR, data);	restore_flags(flags);}static voidMemhscx_empty_fifo(struct BCState *bcs, int count){	u_char *ptr;	struct IsdnCardState *cs = bcs->cs;	long flags;	int cnt;	if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))		debugl1(cs, "hscx_empty_fifo");	if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {		if (cs->debug & L1_DEB_WARN)			debugl1(cs, "hscx_empty_fifo: incoming packet too large");		MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);		bcs->hw.hscx.rcvidx = 0;		return;	}	save_flags(flags);	cli();	ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;	cnt = count;	while (cnt--)		*ptr++ = memreadreg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0);	MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);	ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;	bcs->hw.hscx.rcvidx += count;	restore_flags(flags);	if (cs->debug & L1_DEB_HSCX_FIFO) {		char *t = bcs->blog;		t += sprintf(t, "hscx_empty_fifo %c cnt %d",			     bcs->hw.hscx.hscx ? 'B' : 'A', count);		QuickHex(t, ptr, count);		debugl1(cs, bcs->blog);	}}static voidMemhscx_fill_fifo(struct BCState *bcs){	struct IsdnCardState *cs = bcs->cs;	int more, count, cnt;	int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;	u_char *ptr,*p;	long flags;	if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))		debugl1(cs, "hscx_fill_fifo");	if (!bcs->tx_skb)		return;	if (bcs->tx_skb->len <= 0)		return;	more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;	if (bcs->tx_skb->len > fifo_size) {		more = !0;		count = fifo_size;	} else		count = bcs->tx_skb->len;	cnt = count;	MemwaitforXFW(cs, bcs->hw.hscx.hscx);	save_flags(flags);	cli();	p = ptr = bcs->tx_skb->data;	skb_pull(bcs->tx_skb, count);	bcs->tx_cnt -= count;	bcs->hw.hscx.count += count;	while(cnt--)		memwritereg(cs->hw.diva.cfg_reg, bcs->hw.hscx.hscx ? 0x40 : 0,			*p++);	MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);	restore_flags(flags);	if (cs->debug & L1_DEB_HSCX_FIFO) {		char *t = bcs->blog;		t += sprintf(t, "hscx_fill_fifo %c cnt %d",			     bcs->hw.hscx.hscx ? 'B' : 'A', count);		QuickHex(t, ptr, count);		debugl1(cs, bcs->blog);	}}static inline voidMemhscx_interrupt(struct IsdnCardState *cs, u_char val, u_char hscx){	u_char r;	struct BCState *bcs = cs->bcs + hscx;	struct sk_buff *skb;	int fifo_size = test_bit(HW_IPAC, &cs->HW_Flags)? 64: 32;	int count;	if (!test_bit(BC_FLG_INIT, &bcs->Flag))		return;	if (val & 0x80) {	/* RME */		r = MemReadHSCX(cs, hscx, HSCX_RSTA);		if ((r & 0xf0) != 0xa0) {			if (!(r & 0x80))				if (cs->debug & L1_DEB_WARN)					debugl1(cs, "HSCX invalid frame");			if ((r & 0x40) && bcs->mode)				if (cs->debug & L1_DEB_WARN)					debugl1(cs, "HSCX RDO mode=%d",						bcs->mode);			if (!(r & 0x20))				if (cs->debug & L1_DEB_WARN)					debugl1(cs, "HSCX CRC error");			MemWriteHSCXCMDR(cs, hscx, 0x80);		} else {			count = MemReadHSCX(cs, hscx, HSCX_RBCL) & (				test_bit(HW_IPAC, &cs->HW_Flags)? 0x3f: 0x1f);			if (count == 0)				count = fifo_size;			Memhscx_empty_fifo(bcs, count);			if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {				if (cs->debug & L1_DEB_HSCX_FIFO)					debugl1(cs, "HX Frame %d", count);				if (!(skb = dev_alloc_skb(count)))					printk(KERN_WARNING "HSCX: receive out of memory\n");				else {					memcpy(skb_put(skb, count), bcs->hw.hscx.rcvbuf, count);					skb_queue_tail(&bcs->rqueue, skb);				}			}		}		bcs->hw.hscx.rcvidx = 0;		hscx_sched_event(bcs, B_RCVBUFREADY);	}	if (val & 0x40) {	/* RPF */		Memhscx_empty_fifo(bcs, fifo_size);		if (bcs->mode == L1_MODE_TRANS) {			/* receive audio data */			if (!(skb = dev_alloc_skb(fifo_size)))				printk(KERN_WARNING "HiSax: receive out of memory\n");			else {				memcpy(skb_put(skb, fifo_size), bcs->hw.hscx.rcvbuf, fifo_size);				skb_queue_tail(&bcs->rqueue, skb);			}			bcs->hw.hscx.rcvidx = 0;			hscx_sched_event(bcs, B_RCVBUFREADY);		}	}	if (val & 0x10) {	/* XPR */		if (bcs->tx_skb) {			if (bcs->tx_skb->len) {				Memhscx_fill_fifo(bcs);				return;			} else {				if (bcs->st->lli.l1writewakeup &&					(PACKET_NOACK != bcs->tx_skb->pkt_type))					bcs->st->lli.l1writewakeup(bcs->st, bcs->hw.hscx.count);				dev_kfree_skb_irq(bcs->tx_skb);				bcs->hw.hscx.count = 0; 				bcs->tx_skb = NULL;			}		}		if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {			bcs->hw.hscx.count = 0;			test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);			Memhscx_fill_fifo(bcs);		} else {			test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);			hscx_sched_event(bcs, B_XMTBUFREADY);		}	}}static inline voidMemhscx_int_main(struct IsdnCardState *cs, u_char val){	u_char exval;	struct BCState *bcs;	if (val & 0x01) { // EXB		bcs = cs->bcs + 1;		exval = MemReadHSCX(cs, 1, HSCX_EXIR);		if (exval & 0x40) {			if (bcs->mode == 1)				Memhscx_fill_fifo(bcs);			else {				/* Here we lost an TX interrupt, so				   * restart transmitting the whole frame.				 */				if (bcs->tx_skb) {					skb_push(bcs->tx_skb, bcs->hw.hscx.count);					bcs->tx_cnt += bcs->hw.hscx.count;					bcs->hw.hscx.count = 0;				}				MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);				if (cs->debug & L1_DEB_WARN)					debugl1(cs, "HSCX B EXIR %x Lost TX", exval);			}		} else if (cs->debug & L1_DEB_HSCX)			debugl1(cs, "HSCX B EXIR %x", exval);	}	if (val & 0xf8) {		if (cs->debug & L1_DEB_HSCX)			debugl1(cs, "HSCX B interrupt %x", val);		Memhscx_interrupt(cs, val, 1);	}	if (val & 0x02) {	// EXA		bcs = cs->bcs;		exval = MemReadHSCX(cs, 0, HSCX_EXIR);		if (exval & 0x40) {			if (bcs->mode == L1_MODE_TRANS)				Memhscx_fill_fifo(bcs);			else {				/* Here we lost an TX interrupt, so				   * restart transmitting the whole frame.				 */				if (bcs->tx_skb) {					skb_push(bcs->tx_skb, bcs->hw.hscx.count);					bcs->tx_cnt += bcs->hw.hscx.count;					bcs->hw.hscx.count = 0;				}				MemWriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x01);				if (cs->debug & L1_DEB_WARN)					debugl1(cs, "HSCX A EXIR %x Lost TX", exval);			}		} else if (cs->debug & L1_DEB_HSCX)			debugl1(cs, "HSCX A EXIR %x", exval);	}	if (val & 0x04) {	// ICA		exval = MemReadHSCX(cs, 0, HSCX_ISTA);		if (cs->debug & L1_DEB_HSCX)			debugl1(cs, "HSCX A interrupt %x", exval);		Memhscx_interrupt(cs, exval, 0);	}}static voiddiva_irq_ipac_pci(int intno, void *dev_id, struct pt_regs *regs){	struct IsdnCardState *cs = dev_id;	u_char ista,val;	int icnt=5;	u_char *cfg;	if (!cs) {		printk(KERN_WARNING "Diva: Spurious interrupt!\n");		return;	}	cfg = (u_char *) cs->hw.diva.pci_cfg;	val = *cfg;	if (!(val & PITA_INT0_STATUS))		return; /* other shared IRQ */	*cfg = PITA_INT0_STATUS; /* Reset pending INT0 */	ista = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);Start_IPACPCI:	if (cs->debug & L1_DEB_IPAC)		debugl1(cs, "IPAC ISTA %02X", ista);	if (ista & 0x0f) {		val = memreadreg(cs->hw.diva.cfg_reg, HSCX_ISTA + 0x40);		if (ista & 0x01)			val |= 0x01;		if (ista & 0x04)			val |= 0x02;		if (ista & 0x08)			val |= 0x04;		if (val)			Memhscx_int_main(cs, val);	}	if (ista & 0x20) {		val = 0xfe & memreadreg(cs->hw.diva.cfg_reg, ISAC_ISTA + 0x80);		if (val) {			isac_interrupt(cs, val);		}	}	if (ista & 0x10) {		val = 0x01;		isac_interrupt(cs, val);	}	ista  = memreadreg(cs->hw.diva.cfg_reg, IPAC_ISTA);	if ((ista & 0x3f) && icnt) {		icnt--;		goto Start_IPACPCI;	}	if (!icnt)		printk(KERN_WARNING "DIVA IPAC PCI IRQ LOOP\n");	memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xFF);	memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xC0);}static voiddiva_irq_ipacx_pci(int intno, void *dev_id, struct pt_regs *regs){	struct IsdnCardState *cs = dev_id;	u_char val;	u_char *cfg;	if (!cs) {		printk(KERN_WARNING "Diva: Spurious interrupt!\n");		return;	}	cfg = (u_char *) cs->hw.diva.pci_cfg;	val = *cfg;	if (!(val &PITA_INT0_STATUS)) return; // other shared IRQ  interrupt_ipacx(cs);      // handler for chip	*cfg = PITA_INT0_STATUS;  // Reset PLX interrupt}voidrelease_io_diva(struct IsdnCardState *cs){	int bytecnt;	if ((cs->subtyp == DIVA_IPAC_PCI) || 	    (cs->subtyp == DIVA_IPACX_PCI)   ) {		u_int *cfg = (unsigned int *)cs->hw.diva.pci_cfg;		*cfg = 0; /* disable INT0/1 */ 		*cfg = 2; /* reset pending INT0 */		iounmap((void *)cs->hw.diva.cfg_reg);		iounmap((void *)cs->hw.diva.pci_cfg);		return;	} else if (cs->subtyp != DIVA_IPAC_ISA) {		del_timer(&cs->hw.diva.tl);		if (cs->hw.diva.cfg_reg)			byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */	}	if ((cs->subtyp == DIVA_ISA) || (cs->subtyp == DIVA_IPAC_ISA))		bytecnt = 8;	else		bytecnt = 32;	if (cs->hw.diva.cfg_reg) {		release_region(cs->hw.diva.cfg_reg, bytecnt);	}}static voidreset_diva(struct IsdnCardState *cs){	long flags;	save_flags(flags);	sti();	if (cs->subtyp == DIVA_IPAC_ISA) {		writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x20);		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_POTA2, 0x00);		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, IPAC_MASK, 0xc0);	} else if (cs->subtyp == DIVA_IPAC_PCI) {		unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +					PITA_MISC_REG);		*ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		*ireg = PITA_PARA_MPX_MODE;		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		memwritereg(cs->hw.diva.cfg_reg, IPAC_MASK, 0xc0);	} else if (cs->subtyp == DIVA_IPACX_PCI) {		unsigned int *ireg = (unsigned int *)(cs->hw.diva.pci_cfg +					PITA_MISC_REG);		*ireg = PITA_PARA_SOFTRESET | PITA_PARA_MPX_MODE;		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		*ireg = PITA_PARA_MPX_MODE | PITA_SER_SOFTRESET;		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		MemWriteISAC_IPACX(cs, IPACX_MASK, 0xff); // Interrupts off	} else { /* DIVA 2.0 */		cs->hw.diva.ctrl_reg = 0;        /* Reset On */		byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		cs->hw.diva.ctrl_reg |= DIVA_RESET;  /* Reset Off */		byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);		set_current_state(TASK_UNINTERRUPTIBLE);		schedule_timeout((10*HZ)/1000);		if (cs->subtyp == DIVA_ISA)			cs->hw.diva.ctrl_reg |= DIVA_ISA_LED_A;		else {			/* Workaround PCI9060 */			byteout(cs->hw.diva.pci_cfg + 0x69, 9);			cs->hw.diva.ctrl_reg |= DIVA_PCI_LED_A;		}		byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg);	}	restore_flags(flags);}