?? filter.vhd
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library ieee;
use ieee.std_logic_1164.all;
package mydefine is
type def is array (natural range<>) of std_logic_vector(7 downto 0);
constant rank:integer:=3;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all; --使用定義過的數據類型庫
entity filter is
port(indata:in std_logic_vector(7 downto 0);
outdata:out std_logic_vector(rank-1 downto 0);
en:in std_logic;
clk:in std_logic;
add_en:out std_logic;
rf:in std_logic);
end filter;
architecture beh of filter is
begin
fil:process
variable count:unsigned(3 downto 0):="0000";
variable temp:def(2 downto 0);
variable s:std_logic;
begin
wait until clk'event and clk='0';
if(en='1') then
for i in rank downto 1 loop
temp(i):=temp(i-1);
end loop;
temp(0):=indata;
count:="0000"; --讀入數據
s:='1';
end if;
case count is
when "0001"=>for i in rank-1 downto 0 loop --將讀入的數據轉換為
outdata(i)<=temp(i)(0); --地址
end loop;
if s='1' then
add_en<='1';
end if;
when "0010"=>for i in rank-1 downto 0 loop
outdata(i)<=temp(i)(1);
end loop;
s:='0';
when "0011"=>for i in rank-1 downto 0 loop
outdata(i)<=temp(i)(2);
end loop;
when "0100"=>for i in rank-1 downto 0 loop
outdata(i)<=temp(i)(3);
end loop;
when "0101"=>for i in rank-1 downto 0 loop
outdata(i)<=temp(i)(4);
end loop;
when "0110"=>for i in rank-1 downto 0 loop
outdata(i)<=temp(i)(5);
end loop;
when "0111"=>for i in rank-1 downto 0 loop
outdata(i)<=temp(i)(6);
end loop;
when "1000"=>for i in rank-1 downto 0 loop
outdata(i)<=temp(i)(7);
end loop;
when others=> if rf='1' then add_en<='0';
end if;
end case;
count:=count+1;
end process;
end beh;
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