library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity txmittest is
port(
	tx:out std_logic;
	txclkout:out std_logic;--For test send clok;
	data:in std_logic_vector(7 downto 0);	
	cntout:out std_logic_vector(3 downto 0);
    mclk_16,write:in std_logic
);
end txmittest;

architecture behave of txmittest is 
	signal txclk:std_logic;
	signal txreg:std_logic_vector(7 downto 0);
	signal flagsnd:std_logic;
begin 
txclock:process(mclk_16,flagsnd)
		variable cnt:std_logic_vector(3 downto 0);
		variable flag: std_logic;
begin
if(write='0')then
		cnt:="1110";
elsif(mclk_16'event and mclk_16='1')then
	  if(cnt<"1111")then
			cnt:=cnt+'1';
			flag:='0';
	  elsif(cnt="1111")then 
			cnt:="0000";
			flag:='1';
	  end if;
end if;
	txclk<=flag;
	txclkout<=flag;
end process txclock;

txdata:process(txclk,write) 
     variable cnt1:std_logic_vector(3 downto 0);
begin
	if(write='0')then
  		flagsnd<='1';
		cnt1:="0001";
	elsif(txclk'event and txclk='1')then
CASE cnt1 is 
	when "0000"=>tx<='1';
	when "0001"=>tx<='0';
	when "0010"=>tx<=txreg(0);
	when "0011"=>tx<=txreg(1);
	when "0100"=>tx<=txreg(2);
	when "0101"=>tx<=txreg(3);
	when "0110"=>tx<=txreg(4);
	when "0111"=>tx<=txreg(5);
	when "1000"=>tx<=txreg(6);
	when "1001"=>tx<=txreg(7);
	when "1010"=>tx<='1';
	when others=>tx<='1';
end case;
	if(flagsnd='1')then
		if(cnt1<="1001")then
		 	cnt1:=cnt1+'1';
 		elsif(cnt1>"1001")then
			cnt1:="0000";
			flagsnd<='0';
		end if;
	end if;
end if;
cntout<=cnt1;
end process txdata;

inputdata:process(write)
begin
if(write'event and write='0')then
		txreg<=data;--"10000000";
end if;
end process inputdata;
end behave;