library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity fc is
	port(
		s_clk:in std_logic;
		a:in unsigned(7 downto 0);
		b:in unsigned(7 downto 0);
		result:out std_logic);
end fc;

architecture ar of fc is
	begin
		process
			variable r:signed(8 downto 0);
				begin
					wait until s_clk'event and s_clk='0';
					r:=conv_signed(a-b,9);
					if r>30 then result<='1';
					elsif r<-30
						then result<='1';
					else result<='0';
					end if;
		end process;
end ar;