library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity txmit is
port(
	tx:out std_logic;
	--data:in std_logic_vector(7 downto 0);	
    mclk_16,write:in std_logic
);
end txmit;

architecture behave of txmit is 
	signal writein,txclk:std_logic;
	signal txreg:std_logic_vector(7 downto 0);
begin 
txclock:process(mclk_16)
		variable cnt:std_logic_vector(7 downto 0);
		variable flag: std_logic;
	begin
	if(mclk_16'event and mclk_16='1')then
		if(cnt<"00000111")then
			cnt:=cnt+'1';
		elsif(cnt="00000111")then 
			cnt:="00000000";
			flag:=not flag;
			txreg<="00000111";
		end if;
	end if;
		txclk<=flag;
	end process txclock;

txdata:process(txclk) 
     variable cnt1:std_logic_vector(3 downto 0);
begin
if(txclk'event and txclk='1')then
 if(writein='0')then
	 cnt1:=cnt1+'1';
 elsif(writein='1')then
	 cnt1:="1111";
 end if;
	CASE cnt1 is 
	when "0000"=>tx<='0';
	when "0001"=>tx<=txreg(0);
	when "0010"=>tx<=txreg(1);
	when "0011"=>tx<=txreg(2);
	when "0100"=>tx<=txreg(3);
	when "0101"=>tx<=txreg(4);
	when "0110"=>tx<=txreg(5);
	when "0111"=>tx<=txreg(6);
	when "1000"=>tx<=txreg(7);
	when "1001"=>tx<='1';
	when others=>tx<='1';
	end case;
end if;
end process txdata;

inputdata:process(write)
begin
if(write'event and write='0')then
		--txreg<=data;
end if;
end process inputdata;

writefilter:process(mclk_16)
	variable waittime:std_logic_vector(7 downto 0);
	variable qin:std_logic;
	begin
		if(mclk_16'event and mclk_16='1')then
			if(qin=write)then
				writein<=write;
			else
				writein<='1';
			end if;
			if(waittime<"10000000")then
				waittime:=waittime+'1';
			elsif(waittime="10000000")then
				waittime:="00000000";
  				qin:=write;
			end if;
		end if;
--rxout<=rxs;    --For simulation
	end process;
end behave;