library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_signed.all;

entity RXCVER is
--generic:constant:std_logic;
port(
	mclk_16:in std_logic;--16?baud
	reset:in std_logic;				--??
	rxs:in std_logic;--?,??? rx:Which is Received data,And formerly Rxs is the signal by filter;
	rxrdy:out std_logic;--???????
	--clk,hunt1,rxout:out std_logic;  --test
	data:out std_logic_vector(7 downto 0));
end RXCVER;

architecture behave of rxcver is 
--signal rxs:std_logic;
signal hunt:std_logic;--'1'stands for search for the starting bit;0 stands for being count!
signal mclk:std_logic;--baud;
signal recreg:std_logic_vector(7 downto 0);--?????
signal startbit:std_logic;					--??????
begin
--rxfilter:process(mclk_16)
--variable waittime:std_logic_vector(1 downto 0);
--variable qin:std_logic;
--begin
	--if(mclk_16'event and mclk_16='1')then
		--if(qin=rx)then
			--rxs<=rx;
--			else
--			rxs<='1';
	--	end if;
		--if(waittime<"11")then
			--waittime:=waittime+'1';
--			elsif(waittime="11")then
--			waittime:="00";
	--		qin:=rx;
		--end if;
--		end if;
--rxout<=rxs;    --For simulation
	--end process;

rx_clk:process(mclk_16,startbit)
	variable cnt:std_logic_vector(3 downto 0);
	variable clkflag:std_logic;
begin
 if(mclk_16'event and mclk_16='1')then
	if(startbit='0')then
		cnt:="0000";
		clkflag:='0';
	elsif(startbit='1')then
		if(cnt<"1111") then
			cnt:=cnt+"0001";
			clkflag:='0';
		elsif(cnt="1111")then
			cnt:="0000";
    		clkflag:='1';
		end if;
 	end if;
		mclk<=clkflag;
 end if;
--	clk<=clkflag; --for test;
end process;
hunt_set:process(reset,mclk_16,rxs,hunt)
	variable count1:std_logic_vector(3 downto 0);--?????
	variable count2:std_logic_vector(7 downto 0);
	variable flag:std_logic;
	variable flagvar:std_logic;  --

	begin
	if(reset='1')then
			flag:='1';
			flagvar:='0';
			count1:="0000";
			count2:="00000000";
	else
		if(mclk_16'event and mclk_16='1')then
			if(hunt='1' and rxs='0')then
				count2:="00000000";
				if(count1<"0100")then--Search time is 0 to 4;
					count1:=count1+1;
				elsif(count1>="0100")then
					count1:="0000";
					flag:='0';
				end if;
			elsif(hunt='0')then
				count1:="0000";
				if(count2<="10010100")then	--receive datat time is mclk multiply by 8.
											--The value should be 148=16*8+16-4+8;10010100
					count2:=count2+1;
				  if(count2="10010011")then
					flagvar:='1';--which is for rxrdy;
				  end if;
				elsif(count2>"10010100")then
					count2:="00000000";
					flag:='1';
					flagvar:='0';
				end if;
			end if;
		end if;
	end if;
hunt<=flag;
rxrdy<=flagvar;     --noted
--	hunt1<=flag;    --For test;
startbit<=not flag;
end process;

recv_data:process(mclk,reset)
	variable count:std_logic_vector(3 downto 0);
--	variable flagvar:std_logic;
	begin
if(hunt='1')then
--		flagvar:='0';
		count:="0000";
		recreg<="00000000";
else
	if(mclk'event and mclk='1')then
		 if(count<"1000")then
				count:=count+'1';
				recreg(7)<=rxs;
				recreg(6)<=recreg(7);
				recreg(5)<=recreg(6);
				recreg(4)<=recreg(5);
				recreg(3)<=recreg(4);
				recreg(2)<=recreg(3);
				recreg(1)<=recreg(2);
				recreg(0)<=recreg(1);
		 elsif(count>="1000")then
				count:="0000";
--				flagvar:='1';
		 end if;
	 end if;
end if;
--	rxrdy<=flagvar;
	data<=recreg;
end process;
end behave;