?? fc.vhd
字號:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY fc IS
PORT
(
s_clk : IN std_logic;
a : IN unsigned(7 downto 0);
b : IN unsigned(7 downto 0);
result : OUT std_logic);
END fc;
ARCHITECTURE ar OF fc IS
BEGIN
process
variable r : signed(8 downto 0);
begin
wait until s_clk'event and s_clk='0';
r := conv_signed(a-b,9);
if r >20 then result <= '1';
elsif r <-20 then result <= '1';
else result <= '0';
end if;
end process;
END ar;
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