?? sel2.vhd
字號:
--SEL2 模塊
library ieee;
use ieee.std_logic_1164.all;
entity sel2 is
port(
kin1,kin2: in std_logic;
sel:in std_logic;
fout1,fout2,aout1,aout2: out std_logic
);
end sel2;
architecture beh of sel2 is
begin
process(sel)
begin
case sel is
when '0' =>fout1<=kin1;
fout2<=kin2;
when '1' =>aout1<=kin1;
aout2<=kin2;
when others =>null;
end case;
end process;
end beh;
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