library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity decoder_4_16 is
	port(a1,b1,c1,d1,g2a1,g2b1:in std_logic;
					y1,y2:out std_logic_vector(7 downto 0));
end decoder_4_16;
architecture rtl of decoder_4_16 is
component decoder_3_8
port(a,b,c,e1,e2,e3:in std_logic;
						y:out std_logic_vector(7 downto 0));
end component;
signal g2:std_logic;
begin
	g2<=not d1;
	u1:decoder_3_8 port map(a1,b1,c1,d1,g2a1,g2b1,y1);
	u2:decoder_3_8 port map(a1,b1,c1,g2,g2a1,g2b1,y2);
end rtl;