|cpld7256
input[0] => bustri16:in1_tri.data[0]
input[1] => bustri16:in1_tri.data[1]
input[2] => bustri16:in1_tri.data[2]
input[3] => bustri16:in1_tri.data[3]
input[4] => bustri16:in1_tri.data[4]
input[5] => bustri16:in1_tri.data[5]
input[6] => bustri16:in1_tri.data[6]
input[7] => bustri16:in1_tri.data[7]
input[8] => bustri16:in1_tri.data[8]
input[9] => bustri16:in1_tri.data[9]
input[10] => bustri16:in1_tri.data[10]
input[11] => bustri16:in1_tri.data[11]
input[12] => bustri16:in1_tri.data[12]
input[13] => bustri16:in1_tri.data[13]
input[14] => bustri16:in1_tri.data[14]
input[15] => bustri16:in1_tri.data[15]
input[16] => bustri16:in2_tri.data[0]
input[17] => bustri16:in2_tri.data[1]
input[18] => bustri16:in2_tri.data[2]
input[19] => bustri16:in2_tri.data[3]
input[20] => bustri16:in2_tri.data[4]
input[21] => bustri16:in2_tri.data[5]
input[22] => bustri16:in2_tri.data[6]
input[23] => bustri16:in2_tri.data[7]
input[24] => bustri16:in2_tri.data[8]
input[25] => bustri16:in2_tri.data[9]
input[26] => bustri16:in2_tri.data[10]
input[27] => bustri16:in2_tri.data[11]
input[28] => bustri16:in2_tri.data[12]
input[29] => bustri16:in2_tri.data[13]
input[30] => bustri16:in2_tri.data[14]
input[31] => bustri16:in2_tri.data[15]
output[0] <= latch16:out1_latch.q[0]
output[1] <= latch16:out1_latch.q[1]
output[2] <= latch16:out1_latch.q[2]
output[3] <= latch16:out1_latch.q[3]
output[4] <= latch16:out1_latch.q[4]
output[5] <= latch16:out1_latch.q[5]
output[6] <= latch16:out1_latch.q[6]
output[7] <= latch16:out1_latch.q[7]
output[8] <= latch16:out1_latch.q[8]
output[9] <= latch16:out1_latch.q[9]
output[10] <= latch16:out1_latch.q[10]
output[11] <= latch16:out1_latch.q[11]
output[12] <= latch16:out1_latch.q[12]
output[13] <= latch16:out1_latch.q[13]
output[14] <= latch16:out1_latch.q[14]
output[15] <= latch16:out1_latch.q[15]
output[16] <= latch8:out2_latch.q[0]
output[17] <= latch8:out2_latch.q[1]
output[18] <= latch8:out2_latch.q[2]
output[19] <= latch8:out2_latch.q[3]
output[20] <= latch8:out2_latch.q[4]
output[21] <= latch8:out2_latch.q[5]
output[22] <= latch8:out2_latch.q[6]
output[23] <= latch8:out2_latch.q[7]
va[1] => decode2:addr_decode.data[0]
va[2] => decode2:addr_decode.data[1]
va[3] => ~NO_FANOUT~
va[4] => ~NO_FANOUT~
va[5] => ~NO_FANOUT~
va[6] => ~NO_FANOUT~
va[7] => ~NO_FANOUT~
va[8] => ~NO_FANOUT~
va[9] => ~NO_FANOUT~
va[10] => ~NO_FANOUT~
va[11] => ~NO_FANOUT~
va[12] => ~NO_FANOUT~
va[13] => ~NO_FANOUT~
va[14] => ~NO_FANOUT~
va[15] => ~NO_FANOUT~
va[16] => byte~3.IN0
va[16] => comb~3.IN0
va[17] => byte~1.IN0
va[17] => comb~1.IN0
va[18] => byte~0.IN0
va[18] => comb~0.IN0
va[19] => ~NO_FANOUT~
va[20] => ~NO_FANOUT~
va[21] => ~NO_FANOUT~
va[22] => ~NO_FANOUT~
va[23] => ~NO_FANOUT~
d[0] <= bustri16:in2_tri.tridata[0]
d[0] <= bustri16:in1_tri.tridata[0]
d[1] <= bustri16:in2_tri.tridata[1]
d[1] <= bustri16:in1_tri.tridata[1]
d[2] <= bustri16:in2_tri.tridata[2]
d[2] <= bustri16:in1_tri.tridata[2]
d[3] <= bustri16:in2_tri.tridata[3]
d[3] <= bustri16:in1_tri.tridata[3]
d[4] <= bustri16:in2_tri.tridata[4]
d[4] <= bustri16:in1_tri.tridata[4]
d[5] <= bustri16:in2_tri.tridata[5]
d[5] <= bustri16:in1_tri.tridata[5]
d[6] <= bustri16:in2_tri.tridata[6]
d[6] <= bustri16:in1_tri.tridata[6]
d[7] <= bustri16:in2_tri.tridata[7]
d[7] <= bustri16:in1_tri.tridata[7]
d[8] <= bustri16:in2_tri.tridata[8]
d[8] <= bustri16:in1_tri.tridata[8]
d[9] <= bustri16:in2_tri.tridata[9]
d[9] <= bustri16:in1_tri.tridata[9]
d[10] <= bustri16:in2_tri.tridata[10]
d[10] <= bustri16:in1_tri.tridata[10]
d[11] <= bustri16:in2_tri.tridata[11]
d[11] <= bustri16:in1_tri.tridata[11]
d[12] <= bustri16:in2_tri.tridata[12]
d[12] <= bustri16:in1_tri.tridata[12]
d[13] <= bustri16:in2_tri.tridata[13]
d[13] <= bustri16:in1_tri.tridata[13]
d[14] <= bustri16:in2_tri.tridata[14]
d[14] <= bustri16:in1_tri.tridata[14]
d[15] <= bustri16:in2_tri.tridata[15]
d[15] <= bustri16:in1_tri.tridata[15]
dtack <= <VCC>
sysrst => ~NO_FANOUT~
lword => ~NO_FANOUT~
w_r => comb~7.IN0
w_r => comb~9.IN0
w_r => comb~11.IN0
w_r => comb~12.IN0
as => byte~5.IN0
as => comb~5.IN0
ds1 => ~NO_FANOUT~
ds0 => ~NO_FANOUT~
rd <= rd$latch.DB_MAX_OUTPUT_PORT_TYPE
rden <= rd$latch.DB_MAX_OUTPUT_PORT_TYPE
wr <= wr$latch.DB_MAX_OUTPUT_PORT_TYPE
wren <= wr$latch.DB_MAX_OUTPUT_PORT_TYPE
byte <= byte~5.DB_MAX_OUTPUT_PORT_TYPE
my <= byte~5.DB_MAX_OUTPUT_PORT_TYPE


|cpld7256|decode2:addr_decode
data[0] => lpm_decode:lpm_decode_component.data[0]
data[1] => lpm_decode:lpm_decode_component.data[1]
enable => lpm_decode:lpm_decode_component.enable
eq0 <= lpm_decode:lpm_decode_component.eq[0]
eq1 <= lpm_decode:lpm_decode_component.eq[1]
eq2 <= lpm_decode:lpm_decode_component.eq[2]
eq3 <= lpm_decode:lpm_decode_component.eq[3]


|cpld7256|decode2:addr_decode|lpm_decode:lpm_decode_component
data[0] => decode_3kb:auto_generated.data[0]
data[1] => decode_3kb:auto_generated.data[1]
enable => decode_3kb:auto_generated.enable
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
eq[0] <= decode_3kb:auto_generated.eq[0]
eq[1] <= decode_3kb:auto_generated.eq[1]
eq[2] <= decode_3kb:auto_generated.eq[2]
eq[3] <= decode_3kb:auto_generated.eq[3]


|cpld7256|decode2:addr_decode|lpm_decode:lpm_decode_component|decode_3kb:auto_generated
eq[0] <= cmpr1_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= cmpr2_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= cmpr3_aeb_int.DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= cmpr4_aeb_int.DB_MAX_OUTPUT_PORT_TYPE


|cpld7256|latch16:out1_latch
data[0] => lpm_latch:lpm_latch_component.data[0]
data[1] => lpm_latch:lpm_latch_component.data[1]
data[2] => lpm_latch:lpm_latch_component.data[2]
data[3] => lpm_latch:lpm_latch_component.data[3]
data[4] => lpm_latch:lpm_latch_component.data[4]
data[5] => lpm_latch:lpm_latch_component.data[5]
data[6] => lpm_latch:lpm_latch_component.data[6]
data[7] => lpm_latch:lpm_latch_component.data[7]
data[8] => lpm_latch:lpm_latch_component.data[8]
data[9] => lpm_latch:lpm_latch_component.data[9]
data[10] => lpm_latch:lpm_latch_component.data[10]
data[11] => lpm_latch:lpm_latch_component.data[11]
data[12] => lpm_latch:lpm_latch_component.data[12]
data[13] => lpm_latch:lpm_latch_component.data[13]
data[14] => lpm_latch:lpm_latch_component.data[14]
data[15] => lpm_latch:lpm_latch_component.data[15]
gate => lpm_latch:lpm_latch_component.gate
q[0] <= lpm_latch:lpm_latch_component.q[0]
q[1] <= lpm_latch:lpm_latch_component.q[1]
q[2] <= lpm_latch:lpm_latch_component.q[2]
q[3] <= lpm_latch:lpm_latch_component.q[3]
q[4] <= lpm_latch:lpm_latch_component.q[4]
q[5] <= lpm_latch:lpm_latch_component.q[5]
q[6] <= lpm_latch:lpm_latch_component.q[6]
q[7] <= lpm_latch:lpm_latch_component.q[7]
q[8] <= lpm_latch:lpm_latch_component.q[8]
q[9] <= lpm_latch:lpm_latch_component.q[9]
q[10] <= lpm_latch:lpm_latch_component.q[10]
q[11] <= lpm_latch:lpm_latch_component.q[11]
q[12] <= lpm_latch:lpm_latch_component.q[12]
q[13] <= lpm_latch:lpm_latch_component.q[13]
q[14] <= lpm_latch:lpm_latch_component.q[14]
q[15] <= lpm_latch:lpm_latch_component.q[15]


|cpld7256|latch16:out1_latch|lpm_latch:lpm_latch_component
data[0] => latches[0].DATAIN
data[1] => latches[1].DATAIN
data[2] => latches[2].DATAIN
data[3] => latches[3].DATAIN
data[4] => latches[4].DATAIN
data[5] => latches[5].DATAIN
data[6] => latches[6].DATAIN
data[7] => latches[7].DATAIN
data[8] => latches[8].DATAIN
data[9] => latches[9].DATAIN
data[10] => latches[10].DATAIN
data[11] => latches[11].DATAIN
data[12] => latches[12].DATAIN
data[13] => latches[13].DATAIN
data[14] => latches[14].DATAIN
data[15] => latches[15].DATAIN
gate => latches[15].LATCH_ENABLE
gate => latches[14].LATCH_ENABLE
gate => latches[13].LATCH_ENABLE
gate => latches[12].LATCH_ENABLE
gate => latches[11].LATCH_ENABLE
gate => latches[10].LATCH_ENABLE
gate => latches[9].LATCH_ENABLE
gate => latches[8].LATCH_ENABLE
gate => latches[7].LATCH_ENABLE
gate => latches[6].LATCH_ENABLE
gate => latches[5].LATCH_ENABLE
gate => latches[4].LATCH_ENABLE
gate => latches[3].LATCH_ENABLE
gate => latches[2].LATCH_ENABLE
gate => latches[1].LATCH_ENABLE
gate => latches[0].LATCH_ENABLE
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= latches[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= latches[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= latches[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= latches[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= latches[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= latches[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= latches[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= latches[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= latches[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= latches[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= latches[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= latches[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= latches[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= latches[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= latches[15].DB_MAX_OUTPUT_PORT_TYPE


|cpld7256|latch8:out2_latch
data[0] => lpm_latch:lpm_latch_component.data[0]
data[1] => lpm_latch:lpm_latch_component.data[1]