?? cpld7256.pin
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-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC (Refer to
-- the table below for voltage).
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- NON_MIGRATABLE: This pin cannot be migrated.
---------------------------------------------------------------------------------
Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version
CHIP "cpld7256" ASSIGNED TO AN: EPM7256AETC144-10
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
input[5] : 1 : input : LVTTL : : : Y
input[6] : 2 : input : LVTTL : : : Y
GND : 3 : gnd : : : :
TDI : 4 : input : LVTTL : : : N
input[7] : 5 : input : LVTTL : : : Y
input[8] : 6 : input : LVTTL : : : Y
input[9] : 7 : input : LVTTL : : : Y
input[10] : 8 : input : LVTTL : : : Y
input[11] : 9 : input : LVTTL : : : Y
input[12] : 10 : input : LVTTL : : : Y
input[13] : 11 : input : LVTTL : : : Y
input[14] : 12 : input : LVTTL : : : Y
GND : 13 : gnd : : : :
input[15] : 14 : input : LVTTL : : : Y
input[16] : 15 : input : LVTTL : : : Y
input[17] : 16 : input : LVTTL : : : Y
GND : 17 : gnd : : : :
input[18] : 18 : input : LVTTL : : : Y
input[19] : 19 : input : LVTTL : : : Y
TMS : 20 : input : LVTTL : : : N
input[20] : 21 : input : LVTTL : : : Y
input[21] : 22 : input : LVTTL : : : Y
input[22] : 23 : input : LVTTL : : : Y
VCCIO : 24 : power : : 3.3V : :
input[23] : 25 : input : LVTTL : : : Y
input[24] : 26 : input : LVTTL : : : Y
input[25] : 27 : input : LVTTL : : : Y
input[26] : 28 : input : LVTTL : : : Y
input[27] : 29 : input : LVTTL : : : Y
input[28] : 30 : input : LVTTL : : : Y
input[29] : 31 : input : LVTTL : : : Y
input[30] : 32 : input : LVTTL : : : Y
GND : 33 : gnd : : : :
input[31] : 34 : input : LVTTL : : : Y
GND* : 35 : : : : :
output[0] : 36 : output : LVTTL : : : Y
output[1] : 37 : output : LVTTL : : : Y
output[2] : 38 : output : LVTTL : : : Y
output[3] : 39 : output : LVTTL : : : Y
output[4] : 40 : output : LVTTL : : : Y
output[5] : 41 : output : LVTTL : : : Y
output[6] : 42 : output : LVTTL : : : Y
output[7] : 43 : output : LVTTL : : : Y
output[8] : 44 : output : LVTTL : : : Y
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