/* sysFei82557End.c - system configuration module for fei82557End driver */ /* Copyright 1984-2002 Wind River Systems, Inc. *//*modification history--------------------01d,16jul02,jln  Added PCI device ID for 82559 chip in I82845 (spr 79781) 01c,29may02,pai  Added workaround for H/W errata relating to 82562 PHY                 integrated in i82801BA/M ICH2.01b,07nov01,pai  Updated documentation and routines for new device discovery                 algorithm (SPR# 35716).01a,11oct01,pai  Written from sysNetif.  Added dmh 8255x device discovery                 (SPR# 29068).*/ /*DESCRIPTIONThis is the WRS-supplied configuration module for the VxWorksfei82557End (fei) END driver.  It has routines for initializing deviceresources and provides BSP-specific fei82557End driver routines for anyIntel 82557, 82558, 82559, and 82562 fast Ethernet PCI bus controllersfound on the system.The number of supported devices that can be configured for a particularsystem is finite and is specified by the FEI_MAX_UNITS configurationconstant.  This value, and the internal data structures using it, can bemodified in this file for specific implementations.SEE ALSO: muxLib, endLib, ifLib,\tb "Intel 82557 User's Manual,"\tb "Intel 82558 Fast Ethernet PCI Bus Controller with Integrated PHY,"\tb "Intel 82559 Fast Ethernet Multifunction PCI/Cardbus Controller,"\tb "Intel 82559ER Fast Ethernet PCI Controller,"\tb "Intel PRO100B PCI Adapter Driver Technical Reference."INTERNALThe 8255x MII management interface allows the CPU control over the PHY unitvia a control regsiter in the 8255X.  This register, called the ManagementData Interface (MDI) Control Register, allows driver software to place thePHY in specific modes and query the PHY unit for link status.  The structureof the MDI Control Register is described in the following figure.    +-----+--+--+-----+----------+----------+----------------------+    |31 30|29|28|27 26|25      21|20      16|15                   0|    +-----+--+--+-----+----------+----------+----------------------+    | 0  0| I| R|  OP |  PHYADD  |  REGADD  |         DATA         |    +-----+--+--+-----+----------+----------+----------------------+Where:    Bits     Name              -----------------------------     0-15    Data    16-20    PHY Register Address    21-25    PHY Address    26-27    Opcode    28       Ready    29       Interrupt Enable    30-31    ReservedIn a write command, software places the data bits in the "Data" field,and the 8255x shifts them out to the PHY unit.  In a read command the8255x reads these bits serially from the PHY unit, and software canread them from this location.  The "PHY Register Address" field holdsthe PHY register address.  The "PHY Address" field holds the PHY address.The "Opcode" field has valid values:    01 - MDI write    10 - MDI readAny other values for the Opcode field are reserved.  The "Ready" field isset to '1' by the 8255x at the end of an MDI transaction (for example, aread or a write has been completed).  It should be reset to '0' by softwareat the same time the command is written.  The "Interrupt Enable" field,when set to '1' by software, will cause the 8255x to assert an interruptto indicate the end of an MDI cycle.  The "Reserved" field should alwaysbe set to 00b.This configuration module uses local routines sys557mdioRead() andsys557mdioWrite() as an interface for reading and writing MDI data.  BSPusers should not be using these routines to adjust the PHY independent ofthe driver and configuration routines contained herein.ERRATAFrom the Errata secion of Intel document number 298242-015, 'Intel 82801BAI/O Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile(ICH2-M) Specification Update':    "30.  LAN Microcontroller PCI Protocol Violation     Problem:     When the ICH2/ICH2-M (using the 82562ET PLC) is receiving large files     from a peer LAN device using the 10 Mbps data rate, the ICH2/ICH2-M     can cause a system lock-up.  Specifically, if the LAN controller has     Standby Enable set (EEPROM Word 0Ah bit-1 = 1), while receiving large     files using the 10 Mbps data rate and receives a CU_RESUME command     when it is just entering IDLE state, the ICH2/ICH2-M will cause a PCI     protocol violation (typically by asserting FRAME# and IRDY# together)     within the next few PCI cycles.  This will cause the PCI bus to     lock-up, further resulting in system lock-up.      Implication:     Large file transfers to the ICH2/ICH2-M using 10 Mpbs can cause the     receiving system to lock-up.      Workaround:     Clear EEPROM Word 0Ah bit-1 to 0.  This will result in an increase     power consumption of the ICH2/ICH2-M of ~ 40 mW.      Status:     There are no plans to fix this erratum."The sys557Init() routine implements the specified workaround for thiserrata.*/#if defined(INCLUDE_FEI_END)/* includes */#include <end.h>#include <drv/end/fei82557End.h>/* defines *//* BSP specific FEI ethernet device type constants */#define TYPE_PRO100B_PCI  (1)           /* Intel EtherExpress PRO-100B PCI */#define TYPE_I82557_PCI   (2)           /* Intel 82557 - 82559 */#define TYPE_I82559_PCI   (3)           /* Intel "InBusiness" model */#define TYPE_I82559ER_PCI (4)           /* Intel 82559ER */#define TYPE_I82562_PCI   (5)           /* Intel ICH2 integrated 82562 */#define TYPE_I82562ET_PCI (6)           /* Intel 82562, PCI Revs 1 & 3 *//* EEPROM control bits */#define EE_SK             (0x01)        /* shift clock */#define EE_CS             (0x02)        /* chip select */#define EE_DI             (0x04)        /* chip data in */#define EE_DO             (0x08)        /* chip data out *//* EEPROM opcode */#define EE_CMD_WRITE      (0x05)        /* WRITE opcode, 101 */#define EE_CMD_READ       (0x06)        /* READ  opcode, 110 */#define EE_CMD_ERASE      (0x07)        /* ERASE opcode, 111 *//* EEPROM misc. defines */#define EE_CMD_BITS       (3)           /* number of opcode bits */#define EE_ADDR_BITS      (6)           /* number of address bits */#define EE_DATA_BITS      (16)          /* number of data bits */#define EE_SIZE           (0x40)        /* 0x40 WORDS */#define EE_SIZE_BITS      (6)#define EE_CHECKSUM       (0xbaba)      /* checksum *//* Management Data Interface (MDI) Register */#define MDI_OPC_READ      (0x08000000)  /* MDI Read command opcode */#define MDI_OPC_WRITE     (0x04000000)  /* MDI Write command opcode *//* form an MDI Read command */#define MDI_COMMAND_RD(phyAddr, regAddr) \    (MDI_OPC_READ | ((phyAddr) << 21) | ((regAddr) << 16))/* form an MDI Write command */#define MDI_COMMAND_WR(phyAddr, regAddr, val) \    (MDI_OPC_WRITE | ((phyAddr) << 21) | ((regAddr) << 16) | (val))/* test the MDI "Ready" field */#define MDI_READY_SET(mdiReg)  ((mdiReg) & 0x10000000)/* get the content of the MDI "Data" field */#define MDI_DATA_GET(mdiReg)   ((UINT16)((UINT32)(mdiReg) & 0x0000ffff))/* PCI Vendor IDs for NICs supported by fei82557End */#define FEI_VENDORID_INTEL     (0x8086)      /* Intel PCI vendor ID */#ifndef INTEL_PCI_VENDOR_ID#define INTEL_PCI_VENDOR_ID    (0x8086)      /* Intel PCI vendor ID */#endif /* INTEL_PCI_VENDOR_ID *//* short list of PCI Device IDs for NICs supported by fei82557End */#define FEI_DEVICEID_i82557        (0x1229)      /* 82557 - 82559 */#define FEI_DEVICEID_i82559        (0x1030)      /* The "InBusiness" model */#define FEI_DEVICEID_i82559ER      (0x1209)      /* 82559ER */#define FEI_DEVICEID_i82562        (0x2449)      /* chipset integrated 82562 */#define FEI_DEVICEID_i82559_I82845 (0x103a)      /* 82559 compatible chip in I82845 */  /* typedefs */typedef struct feiResource             /* FEI_RESOURCE */    {    UINT16           eeprom[EE_SIZE];  /* Ethernet Address of this unit */    INT32            timeout;          /* timeout for the self-test */    INT32            str[6];           /* storage for the self-test result */    volatile INT32 * pResults;         /* pointer to the self-test result */    BOOL             initDone;         /* driver has called sys557Init() */    } FEI_RESOURCE;/* locals */LOCAL UINT32 feiUnits = 0;        /* number of FEIs we found *//* This table defines board extended resources */LOCAL FEI_RESOURCE feiResources [FEI_MAX_UNITS] =    {    {{NONE}, NONE, {NONE}, NULL, FALSE},    {{NONE}, NONE, {NONE}, NULL, FALSE},    {{NONE}, NONE, {NONE}, NULL, FALSE},    {{NONE}, NONE, {NONE}, NULL, FALSE}    };/* This table defines board PCI resources */LOCAL PCI_BOARD_RESOURCE feiPciResources [FEI_MAX_UNITS] =    {    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&feiResources[0])    },    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&feiResources[1])    },    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&feiResources[2])    },    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&feiResources[3])    }    };/* English descriptions of supported PHY devices */LOCAL const char * phyNames [] =     {    "None", "i82553-A/B", "i82553-C", "i82503",    "DP83840", "80c240", "80c24", "i82555",    "unknown-8", "unknown-9", "DP83840A", "unknown-11",    "unknown-12", "unknown-13", "unknown-14", "unknown-15"    };enum phyChips     {    NonSuchPhy=0, I82553AB, I82553C, I82503,    DP83840, S80C240, S80C24, I82555, DP83840A=10, UndefinedPhy    };LOCAL const char * connectors [] = {" RJ45", " BNC", " AUI", " MII"};/* forward declarations */LOCAL UINT16  sys557eepromRead (int unit, int loc);LOCAL void    sys557eepromWrite (int unit, int loc, UINT16 data);LOCAL void    sys557eepromWriteBits (int unit, UINT16 data, int bitlen);LOCAL void    sys557eepromChecksumSet (int unit);LOCAL UINT16  sys557mdioRead   (int unit, int phyId, int loc);LOCAL UINT16  sys557mdioWrite  (int unit, int phyId, int loc, UINT16 value);LOCAL int     sys557IntEnable  (int unit);LOCAL int     sys557IntDisable (int unit);LOCAL int     sys557IntAck     (int unit);LOCAL UINT32  sysFeiDevToType  (UINT32, UINT32, UINT8); /* imports */IMPORT FUNCPTR feiEndIntConnect;IMPORT FUNCPTR feiEndIntDisconnect;/********************************************************************************* sys557PciInit - initialize a 82557 PCI ethernet device** This routine performs basic PCI initialization for FEI 82557 PCI ethernet* devices supported by the fei82557End driver.  If supported, the device* memory and I/O addresses are mapped into the local CPU address space* and an internal board-specific resource table is updated with information* on the board type, memory and I/O addresses.** CAVEATS* This routine must be called before the driver attempts to initialize itself* and the physical device via sys557Init().  Also, this routine must be done* prior to MMU initialization, usrMmuInit().** The number of supported devices that can be configured for a particular* system is finite and is specified by the FEI_MAX_UNITS configuration* constant.** RETURNS:* OK, else ERROR when the specified device is not supported, or if* the device could not be mapped into the local CPU memory space.*/STATUS sys557PciInit    (    UINT32  pciBus,      /* store a PCI bus number */    UINT32  pciDevice,   /* store a PCI device number */    UINT32  pciFunc,     /* store a PCI function number */    UINT32  vendorId,    /* store a PCI vendor ID */    UINT32  deviceId,    /* store a PCI device ID */    UINT8   revisionId   /* store a PCI revision ID */    )    {    UINT32  boardType;   /* store a BSP-specific board type constant */    UINT32  memIo32;     /* memory-mapped IO address (BAR 0) */    UINT32  ioBase;      /* IO base address (BAR 1) */    UINT32  flash32;     /* optional flash memory base (BAR 2) */    UINT8   irq;         /* interrupt line number (IRQ) for device */    /* number of physical units exceeded the number supported ? */    if (feiUnits >= FEI_MAX_UNITS)        {        return (ERROR);        }    if ((boardType = sysFeiDevToType (vendorId, deviceId, revisionId))        == BOARD_TYPE_UNKNOWN)        {        return (ERROR);        }    pciConfigInLong  (pciBus, pciDevice, pciFunc,                      PCI_CFG_BASE_ADDRESS_0, &memIo32);    pciConfigInLong  (pciBus, pciDevice, pciFunc,                      PCI_CFG_BASE_ADDRESS_1, &ioBase);    pciConfigInLong  (pciBus, pciDevice, pciFunc,                      PCI_CFG_BASE_ADDRESS_2, &flash32);    memIo32 &= PCI_MEMBASE_MASK;    ioBase  &= PCI_IOBASE_MASK;    flash32 &= PCI_MEMBASE_MASK;    /* map a 4Kb 32-bit non-prefetchable memory IO address decoder */    if (sysMmuMapAdd ((void *)(memIo32 & PCI_DEV_MMU_MSK),        PCI_DEV_ADRS_SIZE, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_PCI) == ERROR)        {        return (ERROR);        }    /* read the IRQ number and vector and save to the resource table */    pciConfigInByte (pciBus, pciDevice, pciFunc,                     PCI_CFG_DEV_INT_LINE, &irq);