sys557eepromWriteBits (unit, EE_CMD_WRITE, 3);    /* (3) Write the Address field */    sys557eepromWriteBits (unit, location, EE_SIZE_BITS);    /* (4) Write the data field */    sys557eepromWriteBits (unit, data, 16);    /* (5) Deactivate the EEPROM */    sysOutWord (iobase + SCB_EEPROM, 0);    sysDelay ();    /* delay */    sysOutWord (iobase + SCB_EEPROM, FEI_EECS);    sysDelay ();    for (i = 0; i < 1000; ++i)        {        if (sysInWord (iobase + SCB_EEPROM) & FEI_EEDO)            break;        for (j = 0; j < 50; ++j)            sysDelay ();        }    sysOutWord (iobase + SCB_EEPROM, 0);    sysDelay ();    /* Disable the write access */    sysOutWord (iobase + SCB_EEPROM, FEI_EECS);    sys557eepromWriteBits (unit, 0x4, 3);    sys557eepromWriteBits (unit, 0, EE_SIZE_BITS);    sysOutWord (iobase + SCB_EEPROM, 0);    sysDelay ();    }/********************************************************************************* sys557eepromWriteBits - write bits to 82557 PCI ethernet device EEPROM** This routine writes a specified <data> item of <bitlen> length-in-bits* to the serial EEPROM of an Intel 8255x device associated with an* END driver <unit> number.** RETURNS: N/A** NOMANUAL*/LOCAL void sys557eepromWriteBits    (    int     unit,           /* END driver unit number */    UINT16  data,           /* the data to write */    int     bitlen          /* the data length in bits */    )    {    UINT16  iobase = (feiPciResources[unit].bar[1]);    UINT16  reg;    UINT16  mask;    /* write the data, MSB first */    for (mask = 1 << (bitlen - 1); mask; mask >>= 1)         {        /* if mask and data then set the EEDI bit on */        reg = ((data & mask) ? (FEI_EECS | FEI_EEDI) : (FEI_EECS));        /* (a) write the bit to the EEDI bit */        sysOutWord (iobase + SCB_EEPROM, reg);        sysDelay();        /* (b) write a '1' to the EESK bit then wait the minumum SK high time */        sysOutWord (iobase + SCB_EEPROM, reg | FEI_EESK);        sysDelay();        /* (c) write a '0' to the EESK bit then wait the minimum SK low time */        sysOutWord (iobase + SCB_EEPROM, reg);        sysDelay();        }    }/********************************************************************************* sys557eepromChecksumSet - set an Intel 825xx EEPROM checksum** This routine computes and writes the checksum for the serial EEPROM* on an Intel 82557, 82558, 82559, or 82562 device associated with the* specified END driver <unit> number.** RETURNS: N/A** NOMANUAL*/LOCAL void sys557eepromChecksumSet    (    int    unit           /* END driver unit number */    )    {    int    ix;    UINT16 sum = 0;    for (ix = 0; ix < EE_SIZE - 1; ix++)         {        sum += sys557eepromRead (unit, ix);        }      sys557eepromWrite (unit, EE_SIZE - 1, (EE_CHECKSUM - sum));    }/********************************************************************************* sys557mdioRead - read from 82557 PCI ethernet Media Data Interface (MDI)** RETURNS: The value read.** NOMANUAL*/LOCAL UINT16 sys557mdioRead    (    int    unit,           /* END driver unit number */    int    phyId,          /* PHY ID (PHY address) */    int    location        /* location to read (PHY register address) */    )    {    UINT16 iobase  = (feiPciResources[unit].bar[1]);    int    timeout = (64 * 4);  /* < 64 usec. to complete, typ 27 ticks */    int    mdi;    /* send command to MDI register and poll for completion */    sysOutLong (iobase + SCB_MDI, MDI_COMMAND_RD(phyId, location));    do  {        sysDelay ();        /* delay for one IO READ cycle */        mdi = sysInLong (iobase + SCB_MDI);        if (--timeout < 0)            printf ("sys557mdioRead() timed out with MDI = %8.8x.\n", mdi);        } while (!MDI_READY_SET(mdi));    return MDI_DATA_GET(mdi);    }/********************************************************************************* sys557mdioWrite - write to 82557 PCI ethernet Media Data Interface (MDI)** RETURNS: The value written.** NOMANUAL*/LOCAL UINT16 sys557mdioWrite    (    int    unit,            /* END driver unit number */    int    phyId,           /* PHY ID (PHY address ) */    int    location,        /* location to write (PHY registe address) */    UINT16 value            /* value to write */    )    {    UINT16 iobase  = (feiPciResources[unit].bar[1]);    int    timeout = (64 * 4);  /* < 64 usec. to complete, typ 27 ticks */    int    mdi;    /* send command to MDI register and poll for completion */    sysOutLong (iobase + SCB_MDI, MDI_COMMAND_WR(phyId, location, value));    do  {        sysDelay ();        /* delay for one IO READ cycle */        mdi = sysInLong (iobase + SCB_MDI);        if (--timeout < 0)            printf ("sys557mdioWrite() timed out with MDI = %8.8x.\n", mdi);        } while (!MDI_READY_SET(mdi));    return MDI_DATA_GET(mdi);    }/********************************************************************************* sys557Show - show 82557 PCI ethernet device configuration ** This routine shows Intel 82557 and compatible device configuration.** RETURNS: N/A*/void sys557Show    (    int        unit        /* END driver unit number */    )    {    UINT16     ioBase;    UINT32     memBase;    UINT32     flashBase = NONE;    UCHAR      etheraddr[6];    int        ix;    int        iy;    PCI_BOARD_RESOURCE const * pRsrc;    FEI_RESOURCE const *       pReso;    if (unit >= feiUnits)        {        printf ("none\n");        return;        }    pRsrc     = &feiPciResources [unit];    pReso     = (FEI_RESOURCE *)(pRsrc->pExtended);    ioBase    = (UINT16)(pRsrc->bar[1]);    memBase   = (pRsrc->bar[0]);    flashBase = (pRsrc->bar[2]);    for (ix = 0, iy = 0; ix < 3; ix++)         {        etheraddr[iy++] = pReso->eeprom[ix];        etheraddr[iy++] = pReso->eeprom[ix] >> 8;        }    printf ("i8255x(%d): Intel EtherExpress Pro 10/100 at %#3x ", unit, ioBase);    for (ix = 0; ix < 5; ix++)        printf ("%2.2X:", etheraddr[ix]);    printf ("%2.2X\n", etheraddr[ix]);    printf ("CSR mem base address = %x, Flash mem base address = %x\n\n",             memBase, flashBase);    printf ("PCI bus no. = %x, device no. = %x, function no. = %x, IRQ = %d\n",            pRsrc->pciBus, pRsrc->pciDevice, pRsrc->pciFunc, pRsrc->irq);    printf ("PCI Device ID = 0x%x\n\n", pRsrc->deviceID);    if (pReso->eeprom[3] & 0x03)        printf ("Receiver lock-up bug exists -- enabling work-around.\n");    printf ("Board assembly %4.4x%2.2x-%3.3d, Physical connectors present:",        pReso->eeprom[8], pReso->eeprom[9]>>8, pReso->eeprom[9] & 0xff);    for (ix = 0; ix < 4; ix++)        if (pReso->eeprom[5] & (1 << ix))            printf ("%s", connectors [ix]);    printf ("\nPrimary interface chip %s PHY #%d.\n",        phyNames[(pReso->eeprom[6]>>8)&15], pReso->eeprom[6] & 0x1f);    if (pReso->eeprom[7] & 0x0700)        printf ("Secondary interface chip %s.\n",                 phyNames[(pReso->eeprom[7]>>8)&7]);    /* We do not show PHY specific register info at this time. */#if  FALSE    for (ix = 0; ix < 2; ix++)        printf ("MDIO register %d is %4.4x.\n",                ix, sys557mdioRead (unit, pReso->eeprom[6] & 0x1f, ix));    for (ix = 5; ix < 7; ix++)        printf ("MDIO register %d is %4.4x.\n",                ix, sys557mdioRead (unit, pReso->eeprom[6] & 0x1f, ix));    printf ("MDIO register %d is %4.4x.\n",            25, sys557mdioRead (unit, pReso->eeprom[6] & 0x1f, 25));#endif  /* FALSE */    if (pReso->timeout < 0)         {                /* Test optimized out. */        printf ("Self test failed, status %8.8x:\n"                " Failure to initialize the i8255x.\n"                " Verify that the card is a bus-master capable slot.\n",                pReso->pResults[1]);        }    else         {        printf ("General self-test: %s.\n"                " Serial sub-system self-test: %s.\n"                " Internal registers self-test: %s.\n"                " ROM checksum self-test: %s (%#8.8x).\n",                pReso->pResults[1] & 0x1000 ? "failed" : "passed",                pReso->pResults[1] & 0x0020 ? "failed" : "passed",                pReso->pResults[1] & 0x0008 ? "failed" : "passed",                pReso->pResults[1] & 0x0004 ? "failed" : "passed",                pReso->pResults[0]);        }    }/********************************************************************************* sysFeiDevToType - convert PCI Vendor and Device IDs to a device type** Given <vendorId>, <deviceId>, and <revisionId> values read from PCI Vendor* and Device ID registers in PCI configuration space, this routine will* attempt to map the IDs to an 8255x device type value defined in this file.** RETURNS:* A board type value which will be one of** .IP* TYPE_I82557_PCI* .IP* TYPE_I82559_PCI* .IP* TYPE_I82559ER_PCI* .IP* TYPE_I82562_PCI* .IP* TYPE_I82562ET_PCI* .LP** NOTE* The TYPE_I82562ET_PCI constant is used specifically to identify the* Intel 82562ET LAN controller integrated in i82801BA (ICH2) and i82801BAM* (ICH2-M) devices.  As noted in the Specification Update for these* devices, document number 298242-015, the PCI Revsion ID values for the* integrated LAN controller are 1 and 3.** BOARD_TYPE_UNKNOWN will be returned if the Device ID does not map to* a supported board type.** NOMANUAL*/LOCAL UINT32 sysFeiDevToType    (    UINT32 vendorId,    /* specifies a PCI Vendor ID value */    UINT32 deviceId,    /* specifies a PCI Device ID value */    UINT8  revisionId   /* specifies a PCI Revision ID value */    )    {    /* At the moment, we are only supporting vendor Intel */    if (vendorId == FEI_VENDORID_INTEL)        {        switch (deviceId)            {            case FEI_DEVICEID_i82557:                return (TYPE_I82557_PCI);            case FEI_DEVICEID_i82559:            case FEI_DEVICEID_i82559_I82845:                  return (TYPE_I82559_PCI);            case FEI_DEVICEID_i82559ER:                return (TYPE_I82559ER_PCI);            case FEI_DEVICEID_i82562:                if ((revisionId == 1) || (revisionId == 3))                    {                    return (TYPE_I82562ET_PCI);                    }                return (TYPE_I82562_PCI);            default:                break;            }        }    return (BOARD_TYPE_UNKNOWN);    }#endif /* INCLUDE_FEI_END */