?? atapi.h
字號:
extern BYTE StringDscrOffset;
extern BYTE UserDscrOffset;
extern BYTE IntrfcSubClassFullSpeedOffset;
extern BYTE DscrEndOffset;
extern BYTE SerialNumberStringDscrOffset;
extern BYTE SerialNumberIndexOffset;
extern BYTE IntrfcClassFullSpeedOffset;
extern BYTE PIDOffset;
extern BYTE VIDOffset;
extern BYTE CSMGeneralDscrOffset;
extern BYTE CSMChannelDscrOffset;
extern BYTE CSMCSMDscrOffset;
extern BYTE CSMCSMVDscrOffset;
extern BYTE FullSpeedInterfaceDscrBreakOffset;
extern BYTE HighSpeedInterfaceDscrBreakOffset;
extern BYTE HIDDscrOffset;
extern BYTE HIDReportDscrOffset;
extern BYTE HIDReportDscrLen;
extern BYTE SerialNumberIndexOffset;
extern void powerOn();
extern void powerOff();
extern MX2_CONFIG_DATA xdata mx2_config_data;
extern bit bShortPacketSent;
extern bit bExtAddrSupport;
extern bit mfgMode;
extern BYTE AlternateSetting; // Alternate settings
extern BYTE Configuration; // Current configuration
extern idata BYTE prevCmd[12];
extern bit attemptFastRead;
extern bit attemptFastWrite;
extern bit attemptFastScsi;
extern WORD gSectorcount;
extern idata DWORD prevDataTransferLen;
extern bit mfgMode;
extern char sensePtr;
extern const char code senseCRCError[] ; // Set on CRC error. Causes host to retry
extern const char code senseInvalidFieldInCDB[] ; // 300 calls this InvalidCommandField
extern const char code senseOk[] ;
extern const char code senseNoMedia[] ;
extern const char code senseWriteFault[] ;
extern const char code senseReadError[] ;
extern const char code senseAddrNotFound[] ;
extern const char code senseInvalidOpcode[] ;
extern const char code senseInvalidLBA[] ;
extern const char code senseInvalidParameter[] ;
extern const char code senseCantEject[] ;
extern const char code senseMediaChanged[] ;
extern const char code senseDeviceReset[] ; // Initial value. Set in ATARESET.c
extern const char code senseWriteProtected[] ;
extern const char code WaveDataPioUDMA[128+64];
extern BYTE intrfcSubClass;
extern BYTE udmaErrorCount;
extern volatile BYTE seconds;
extern volatile BYTE hertz61ticks;
// support for higher PIO modes
#define PIO4 0x02
#define PIO3 0x01
#define PIO_MODE1 0x09
#define PIO_MODE2 0x0A
#define PIO_MODE3 0x0B
#define PIO_MODE4 0x0C
#define dataTransferLenMSW ((WORD *) (&dataTransferLen))[0]
#define dataTransferLen23W ((WORD *) (&dataTransferLen2SB))[0]
#define dataTransferLenLSW ((WORD *) (&dataTransferLen))[1]
#define dataTransferLenMSB ((BYTE *) (&dataTransferLen))[0]
#define dataTransferLen2SB ((BYTE *) (&dataTransferLen))[1]
#define dataTransferLen3SB ((BYTE *) (&dataTransferLen))[2]
#define dataTransferLenLSB ((BYTE *) (&dataTransferLen))[3]
#define USBS_PASSED 0
#define USBS_FAILED 1
#define USBS_PHASE_ERROR 2
#define IN_MASS_STORAGE_CLASS_RESET (((bmHSNAK & EP0CS) && (SETUPDAT[1] == SC_MASS_STORAGE_RESET)))
// Local defines from the mass storage class spec
#define SC_MASS_STORAGE_RESET 0xff
#define SC_GET_MAX_LUN 0xfe
#define CBW_TAG 4
#define CBW_DATA_TRANSFER_LEN_LSB 8
#define CBW_DATA_TRANSFER_LEN_MSB 9
#define CBW_FLAGS 12
#define CBW_FLAGS_DIR_BIT 0x80
#define CBW_LUN 13
#define CBW_CBW_LEN 14
#define CBW_CBW_LEN_MASK 0xf
#define CBW_DATA_START 15
#define USB_MS_RBC_SUBCLASS 1
#define USB_MS_CD_ROM_SUBCLASS 2
#define USB_MS_SCSI_TRANSPARENT_SUBCLASS 6
// Cypress Vendor Specific Config CB defines
#define CONFIG_CB_COMMAND 0x24
#define CONFIG_CB_SUBCOMMAND_EEPROM_RW 0x26
#define CONFIG_CB_SUBCOMMAND_MFG 0x27
#define CONFIG_CB_SUBCOMMAND_OFFSET 0x10
#define CONFIG_CB_EEPROM_ADDR_LSB 0x13
#define ATACB_COMMAND 0x24
#define MX2_EEPROM_SIGNATURE 0x4D4D
#define AT2LP_EEPROM_SIGNATURE 0x534b
// Local defines for the mass storage device
#define PROCESS_CBW_TIMEOUT_RELOAD 0x7000
#define HS_BULK_PACKET_SIZE 0x200
#define FS_BULK_PACKET_SIZE 0x40
#define min(a,b) (((a)<(b))?(a):(b))
#define max(a,b) (((a)>(b))?(a):(b))
// Wait for the drive interrupt macro
#if REVC_4611_BOARD
#define WAIT_FOR_INTRQ() {if(!bCOMPLIANCE_MODE){WAKEUPCS = bmWU | bmWUEN; while((WAKEUPCS & 0x40)) {WAKEUPCS = bmWU | bmWUEN;}}}
#else // AT2LP_PINOUT
#define WAIT_FOR_INTRQ() {if(!bCOMPLIANCE_MODE){while (!(IOA & 1)) ; }}
#endif
#define VBUS_POWERED (((VBUSPWRD && bBIG_PACKAGE) || (((BYTE xdata *) pFullSpeedConfigDscr)[CONFIG_DSCR_POWER_OFFSET]) > 2))
#define PIO_ADDR_COMMAND 7
#define PIO_ADDR_DATA 0
#define ATAPI_INTRQ (PINSA & 0x01)
#define ATAPI_STATUS_BUSY_BIT 0x80
// #define ATAPI_STATUS_DRDY_BIT 0x40 Don't use this bit! It's not set after an A0 command!
#define ATAPI_STATUS_DF_BIT 0x20
#define ATAPI_STATUS_DSC_BIT 0x10
#define ATAPI_STATUS_DRQ_BIT 0x08
#define ATAPI_STATUS_CORR_BIT 0x04
#define ATAPI_STATUS_INDEX_BIT 0x02
#define ATAPI_STATUS_ERROR_BIT 0x01
// Errors for WRITE DMA
#define ATAPI_ERROR_ICRC_BIT 0x80
#define ATAPI_ERROR_WP_BIT 0x40
#define ATAPI_ERROR_MEDIA_CHANGED_BIT 0x20
#define ATAPI_ERROR_ABRT_BIT 0x04
#define ATAPI_ERROR_NO_MEDIA_BIT 0x02
#define ATA_SECTOR_SIZE 0x200
#define IDE_COMMAND_ID_DEVICE 0xec
#define IDE_ID_SERIAL_LEN 20
#define IDE_ID_TOTAL_SECTORS_LSW 60*2
#define IDE_ID_TOTAL_SECTORS_MSW 61*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_LSW 100*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_2SW 101*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_3SW 102*2
#define IDE_ID_TOTAL_48_BIT_SECTORS_MSW 103*2
#define ATAPI_INQUIRY_SERIAL 10*2
#define ATAPI_COMMAND_ID_DEVICE 0xa1
#define ATAPI_COMMAND_ATAPI_PACKET 0xa0
#define ATAPI_COMMAND_SOFT_RESET 0x08
#define ATAPI_COMMAND_CHECK_POWER 0xe5
#define ATAPI_COMMAND_EXEC_DIAG 0x90
#define ATAPI_COMMAND_IDLE 0xe3
#define ATAPI_COMMAND_IDLE_IMMED 0xe1
#define ATAPI_COMMAND_NOP 0x00
#define ATAPI_COMMAND_SERVICE 0xa2
#define ATAPI_COMMAND_SET_FEATURES 0xef
#define SET_FEATURES_WRITE_CACHE_DISABLE 0x82
#define SET_FEATURES_WRITE_CACHE_ENABLE 0x02
#define ATAPI_PACKET_LOAD_UNLOAD 0xa6
#define ATAPI_CONTROL_REG_SOFT_RESET 4
#define ATAPI_CONTROL_REG_DEFAULT 8
// Converted RBC commands
#define ATA_COMMAND_READ_10 0x20
#define ATA_COMMAND_READ_10_EXT 0x24
#define ATA_COMMAND_WRITE_10 0x30
#define ATA_COMMAND_WRITE_10_EXT 0x34
#define ATA_COMMAND_VERIFY_10 0x40
#define ATA_COMMAND_VERIFY_10_EXT 0x42
#define ATA_COMMAND_DMAREAD_RETRY 0xC8
#define ATA_COMMAND_DMAREAD_RETRY_EXT 0x25
// #define ATA_COMMAND_DMAREAD_NORETRY 0xC9 Obsolete in ATA-6
#define ATA_COMMAND_DMAWRITE_RETRY 0xCA
#define ATA_COMMAND_DMAWRITE_RETRY_EXT 0x35
// #define ATA_COMMAND_DMAWRITE_NORETRY 0xCB Obsolete in ATA-6
#define ATA_COMMAND_SEEK 0x70
#define ATA_COMMAND_MEDIA_LOCK 0xde
#define ATA_COMMAND_MEDIA_UNLOCK 0xdf
#define ATA_COMMAND_FLUSH_CACHE 0xe7
#define ATA_COMMAND_MEDIA_EJECT 0xed
#define ATA_COMMAND_STANDBY_IMMEDIATE 0xe0
#define ATA_COMMAND_SLEEP 0xe6
// Still unconverted RBC commands
#define ATA_COMMAND_INQUIRY 0x12
#define ATA_COMMAND_MODE_SELECT_6 0x15
#define ATA_COMMAND_MODE_SENSE_6 0x1A
#define ATA_COMMAND_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E
#define ATA_COMMAND_TEST_UNIT_READY 0x00
#define ATA_COMMAND_WRITE_BUFFER 0x3B
// Optional RBC commands
#define ATA_COMMAND_NOP 0x00
#define ATA_COMMAND_FORMAT_UNIT 0x04
#define ATA_COMMAND_PERSISTENT_RESERVE_IN 0x5E
#define ATA_COMMAND_PERSISTENT_RESERVE_OUT 0x5F
#define ATA_COMMAND_RELEASE_6 0x17
#define ATA_COMMAND_REQUEST_SENSE 0x03
#define ATA_COMMAND_RESERVE_6 0x16
#define ATA_COMMAND_SYNCHRONIZE_CACHE 0x35
// Fields in the INQUIRY
#define SCSI_INQUIRY_DEVICE_CLASS 0
#define SCSI_INQUIRY_REMOVABLE_BIT 0x80
#define SCSI_INQUIRY_REMOVABLE_BYTE 1
#define ATAPI_INQUIRY_REMOVABLE_BYTE 0
#define SCSI_INQUIRY_DATA_FORMAT 3
#define SCSI_INQUIRY_MANUFACTURER 8
#define ATAPI_INQUIRY_MANUFACTURER 27
#define SCSI_INQUIRY_MANUFACTURER_LEN 24
#define ATAPI_INQUIRY_REVISION 73
#define SCSI_INQUIRY_REVISION 32
#define SCSI_INQUIRY_REVISION_LEN 4
#define SCSI_IDENTIFY_LEN 44
// Fields in the structure returned by the IDENTIFY DEVICE (ECh) and
// IDENTIFY PACKET DEVICE (A1h) commands (BYTE offsets)
#define IDENTIFY_FIELD_VALIDITY 53*2
#define IDENTIFY_DMA_MODES 63*2
#define IDENTIFY_ADVANCED_PIO 64*2
#define IDENTIFY_48BIT_ADDRESSING 83*2
#define IDENTIFY_COMMAND_SET_SUPPORT 83*2
#define IDENTIFY_COMMAND_SET_ENABLED 86*2
#define IDENTIFY_UDMA_MODES 88*2
#define IDENTIFY_NUM_CYLINDERS_LSB 54*2
#define IDENTIFY_NUM_CYLINDERS_MSB IDENTIFY_NUM_CYLINDERS_LSB+1
#define IDENTIFY_NUM_HEADS 55*2
#define IDENTIFY_NUM_SECT_PER_TRACK 56*2
// DMA supported modes bits from IDENTIFY DEVICE
#define DMA_MODE0 0x01
#define DMA_MODE1 0x02
#define DMA_MODE2 0x04
// UDMA supported modes bits from IDENTIFY DEVICE
#define UDMA_MODE0 0x01
#define UDMA_MODE1 0x02
#define UDMA_MODE2 0x04
#define UDMA_MODE3 0x08
#define UDMA_MODE4 0x10
#define UDMA_MODE5 0x20
// Advanced Power Management support/enabled bit from IDENTIFY
#define APM_FEATURE 0x08
// SET FEATURE sub-command codes
#define SET_FEATURE_TRANSFER_MODE 0x03
#define SET_FEATURE_APM_ENABLE 0x05
// Transfer mode settings
#define TRANSFER_MODE_DEFAULT 0x00
#define TRANSFER_MODE_PIO1 0x09
#define TRANSFER_MODE_PIO2 0x0A
#define TRANSFER_MODE_PIO3 0x0B
#define TRANSFER_MODE_PIO4 0x0C
#define TRANSFER_MODE_DMA0 0x20
#define TRANSFER_MODE_DMA1 0x21
#define TRANSFER_MODE_DMA2 0x22
#define TRANSFER_MODE_UDMA0 0x40
#define TRANSFER_MODE_UDMA1 0x41
#define TRANSFER_MODE_UDMA2 0x42
#define TRANSFER_MODE_UDMA3 0x43
#define TRANSFER_MODE_UDMA4 0x44
#define TRANSFER_MODE_UDMA5 0x45
// Local ATAPI defines -- Command register block
#define ATAPI_DATA_REG (DA(0)|CS(2))
#define ATAPI_ERROR_REG (DA(1)|CS(2))
#define ATAPI_FEATURE_REG (DA(1)|CS(2))
#define ATAPI_INT_CAUSE_REG (DA(2)|CS(2))
#define ATAPI_BYTE_COUNT_LSB (DA(4)|CS(2))
#define ATAPI_BYTE_COUNT_MSB (DA(5)|CS(2))
#define ATAPI_DRIVESEL_REG (DA(6)|CS(2))
#define ATAPI_STATUS_REG (DA(7)|CS(2))
#define ATAPI_COMMAND_REG (DA(7)|CS(2))
#define ATAPI_NULL_REG (DA(7)|CS(3))
// Local ATAPI defines -- Control register block
#define ATAPI_ALT_STATUS_REG (DA(6)|CS(1))
#define ATAPI_CONTROL_REG (DA(6)|CS(1))
// IDE registers -- Overlay on the ATAPI register space
#define ATA_DATA_REG (DA(0)|CS(2))
#define ATA_ERROR_REG (DA(1)|CS(2))
#define ATA_SECTOR_COUNT_REG (DA(2)|CS(2))
#define ATA_LBA_LSB_REG (DA(3)|CS(2))
#define ATA_LBA_2SB_REG (DA(4)|CS(2))
#define ATA_LBA_MSB_REG (DA(5)|CS(2))
#define ATA_DRIVESEL_REG (DA(6)|CS(2))
#define ATA_COMMAND_REG (DA(7)|CS(2))
#define pDeviceDscr ((WORD)(halfKBuffer + (BYTE)&DeviceDscrOffset))
#define pDeviceQualDscr ((WORD)(halfKBuffer + (BYTE)&DeviceQualDscrOffset))
#define pFullSpeedConfigDscr ((WORD)(halfKBuffer + (BYTE)&FullSpeedConfigDscrOffset))
//#define WaveDataPio0 (WaveDataPio4+4)
#define senseCRCError 0
#define senseInvalidFieldInCDB 1
#define senseOk 2
#define senseNoMedia 3
#define senseWriteFault 4
#define senseReadError 5
#define senseAddrNotFound 6
#define senseInvalidOpcode 7
#define senseInvalidLBA 8
#define senseInvalidParameter 9
#define senseCantEject 0xa
#define senseMediaChanged 0xb
#define senseDeviceReset 0xc
#define senseWriteProtected 0xd
#define DSCR_DEVICE_LEN 18
#define DSCR_CONFIG_LEN 9
#define DSCR_INTRFC_LEN 9
#define DSCR_ENDPNT_LEN 7
#define DSCR_DEVQUAL_LEN 10
#define DSCR_CONFIG 2
#define DSCR_INTRFC 4
#define DSCR_ENDPNT 5
#define CONFIG_DSCR_ATTRIB_OFFSET 7
#define CONFIG_DSCR_POWER_OFFSET 8
#define EP_DSCR_LEN_LSB_OFFSET 4
#define EP_DSCR_LEN_MSB_OFFSET 5
#define EEPROM_ADDR 0x51
#define EEPROM_PAGE_SIZE 8
#define MAX_LUN 2
// HID class request codes
#define SC_HID_SET_REPORT 0x09
#define SC_HID_SET_IDLE 0x0A
#define CONFIG_SPACE_START 0x3f00 /* start of config area in EEPROM */
#endif
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -