Flow report for divider
Tue Aug 23 16:26:06 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+-------------------------+------------------------------------------+
; Flow Status             ; Successful - Tue Aug 23 16:26:05 2005    ;
; Quartus II Version      ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name           ; divider                                  ;
; Top-level Entity Name   ; divider                                  ;
; Family                  ; ACEX1K                                   ;
; Device                  ; EP1K100QC208-3                           ;
; Timing Models           ; Final                                    ;
; Met timing requirements ; Yes                                      ;
; Total logic elements    ; 46 / 4,992 ( < 1 % )                     ;
; Total pins              ; 27 / 147 ( 18 % )                        ;
; Total memory bits       ; 0 / 49,152 ( 0 % )                       ;
; Total PLLs              ; 0                                        ;
+-------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 08/23/2005 16:25:42 ;
; Main task         ; Compilation         ;
; Revision Name     ; divider             ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:04     ;
; Fitter               ; 00:00:13     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:02     ;
; Total                ; 00:00:21     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off divider -c divider
quartus_fit --read_settings_files=off --write_settings_files=off divider -c divider
quartus_asm --read_settings_files=off --write_settings_files=off divider -c divider
quartus_tan --read_settings_files=off --write_settings_files=off divider -c divider