/*******************************************************************************
Copyright(c) 2000 - 2003 Analog Devices. All Rights Reserved.
Developed by Blackfin DSP software Group, IPDC, Bangalore, India
for Blackfin DSPs.
By using this module you agree to the terms of the Analog Devices License
Agreement for DSP Software. 
*******************************************************************************
Module name     :   iir_fr24_df1.asm
Label name      :   __iir_fr24_df1
Version         :   1.1

Change History  :
                Version     Date        Author          Comments
                1.1         02/17/2003  Swarnalatha     Tested with
                                                        VDSP++ 3.0 on 
                                                        ADSP-21535 Rev.0.2
                1.0        12/17/2000   Manoj&Siva      Original
                
Description     :   This program implements a second order biquad,canonical form,
                    IIR filter for 1.31 format data and coefficients. The coeff
                    buffer that is passed should be in the order b2,b1,b0,a2,a1. 
                    The value of a0 is unity. The delay line buffer must be 
                    ordered as d(n-2),d(n-1) for each stage. The equations 
                    implemented are d(n) = x(n) - a1 * d(n-1) - a2 * d(n-2)
					y(n) = b0 * d(n) + b1 * d(n-1) +b2 * d(n-2)
Note		   :	The coefficients b's and a's generated using MATLAB can be 
                    used as it is. However, the 'a' coefficients have to be 
                    negated in some cases where the coefficient generation 
                    software by itself gives negative 'a' coefficients. 
	
Implementation :    (d.h*c.h) + (d.h*c.l+c.h*d.l) >>> 16
                    where d is data and c is the coefficient
Prototype      :
                    Void _iir_fr24_df1
                            (
                            fract32 *,      //Pointer to the input
                            fract32 *,      //Pointer to the output
                            fract32 *,      //Pointer to the coefficients
                            fract32 *,      //Pointer to the delay line
                            int             //Number of samples
                            )
Registers Used  :   A0, A1, R0-R3, I0-I3, L0-L3, M0, B1, B2, P0, LC0
	
Performance     :
                    Initializations : 23 Cycles
	               Core Cycle Count: 12 * N Cycles
	               where N is the number of data samples
	               For N=128, Cycle count=1712 cycles
*******************************************************************************/

.section  L1_code;
.global __iir_fr24_df1;
.align 8;
__iir_fr24_df1:
      
	I0=R0;		            //Address of Input
	L0=0;
	L3=0;
	I1=R1;		            //Address of Output
	B1=R1;
	R0=[SP+16];	            //No. of samples
	R0=R0 << 2 || NOP;
	I2=R2;		            //Address of the Filter Biquad
	L1=R0;
 	R1=[SP+12];
	I3=R1;		            //Address of delay line
	P0=[SP+16];	            //No. of Samples
	B2=R2;
	L2=20;
	
	M0=-8;
	R1=[I0++] || R2=[I2++];	//Read First Input, b0
	A0=R1.H*R2.H , A1=R1.H*R2.L (M)  || R0=[I3] || I1-=4;	
	                        //Read x(-1)
    A1+=R2.H*R1.L (M)  || R2=[I2++];	
                            //Update X(-1). Fetch b1	

  	LSETUP(IIR_ST,IIR_END) LC0=P0;
  	                        //Loop setup for number of input samples

IIR_ST:
		A0+=R0.H*R2.H, A1+=R0.H*R2.L (M) || [I3++]=R1;	
		                    //Read x(-2)
		A1+=R2.H*R0.L (M) || R1=[I3]  || R2=[I2++];	
		                    //Update X(-2). Fetch b2
		A0+=R1.H*R2.H , A1+=R1.H*R2.L (M) ||[I3++]=R0; 
		A1+=R2.H*R1.L (M) || R0=[I3++] || R2=[I2++];	
		                    //Read y(-1). Fetch a1
		A0-=R0.H*R2.H, A1-=R0.H*R2.L (M)|| R1=[I3]  || [I1++]=R3;
		                    //Read y(-2)
		A1-=R2.H*R0.L (M) ||[I3--]=R0  || R2=[I2++];
		                    //Update Y(-2). Fetch a2
		R0=(A0-=R1.H*R2.H), A1-=R1.H*R2.L (M); 
		R1=(A1-=R2.H*R1.L) (M);
		R3=R1>>>15;
		R3=R0+R3 (S) || R1=[I0++] || R2=[I2++];
		A0=R1.H*R2.H , A1=R1.H*R2.L (M)   || [I3++M0]=R3;
IIR_END: 
        A1+=R2.H*R1.L (M)  || R0=[I3] || R2=[I2++]  ;	
                            //Update X(-1). Fetch b1
	
		
	[I1++]=R3;
	L1=0;
	L2=0;
	RTS;