?? initsystem.h
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/***************************************************
公司: 好易通科技有限公司
產品名: TETRA數字集群終端
CPU: OMAP5910
功能: 初始化系統
作者: 袁林
編寫時間: 2005.01.12
修改時間： 2005.06.06
****************************************************/
#ifndef __INITSYSTEM_H__
#define __INITSYSTEM_H__
#include "type.h"
#include "io.h"
/*typedef enum
{
False= 0, True=1
}boolean_t;
#define BOOL boolean_t*/
#define NO False
#define YES True
#define DISABLE False
#define ENABLE True
#define NOT_OK False
#define IS_OK True
#define HIGH_LEVEL True
#define DPLL_COMMON_DIVIDER (UWORD8)2
// ARM RHEA PERIPHERALS MAPPING
#define ARM_PUBLIC_RHEA_STROBE_0 0xFFFB0000
#define ARM_PUBLIC_RHEA_STROBE_1 0xFFFC0000
#define ARM_PRIVATE_RHEA_STROBE_0 0xFFFD0000
#define ARM_PRIVATE_RHEA_STROBE_1 0xFFFE0000
#define RHEA_OFFSET_CS0 0x0000
#define RHEA_OFFSET_CS1 0x0800
#define RHEA_OFFSET_CS2 0x1000
#define RHEA_OFFSET_CS3 0x1800
#define RHEA_OFFSET_CS4 0x2000
#define RHEA_OFFSET_CS5 0x2800
#define RHEA_OFFSET_CS6 0x3000
#define RHEA_OFFSET_CS7 0x3800
#define RHEA_OFFSET_CS8 0x4000
#define RHEA_OFFSET_CS9 0x4800
#define RHEA_OFFSET_CS10 0x5000
#define RHEA_OFFSET_CS11 0x5800
#define RHEA_OFFSET_CS12 0x6000
#define RHEA_OFFSET_CS13 0x6800
#define RHEA_OFFSET_CS14 0x7000
#define RHEA_OFFSET_CS15 0x7800
#define RHEA_OFFSET_CS16 0x8000
#define RHEA_OFFSET_CS17 0x8800
#define RHEA_OFFSET_CS18 0x9000
#define RHEA_OFFSET_CS19 0x9800
#define RHEA_OFFSET_CS20 0xA000
#define RHEA_OFFSET_CS21 0xA800
#define RHEA_OFFSET_CS22 0xB000
#define RHEA_OFFSET_CS23 0xB800
#define RHEA_OFFSET_CS24 0xC000
#define RHEA_OFFSET_CS25 0xC800
#define RHEA_OFFSET_CS26 0xD000
#define RHEA_OFFSET_CS27 0xD800
#define RHEA_OFFSET_CS28 0xE000
#define RHEA_OFFSET_CS29 0xE800
#define RHEA_OFFSET_CS30 0xF000
#define RHEA_OFFSET_CS31 0xF800
/* configure register address */
#define CONFIGURATION_BASE_ADDRESS (ARM_PRIVATE_RHEA_STROBE_1 + RHEA_OFFSET_CS2) //0xFFFE1000
#define BASE_ADDRESS_INT_PERI (ARM_PRIVATE_RHEA_STROBE_1 + RHEA_OFFSET_CS24) //0xFFFE0000+0xC000
#define MEM_SIZE_IN_BYTES 0x100
#define MEM_ARM_LCD_CONTROLLER_ADDR (BASE_ADDRESS_INT_PERI) //0xFFFEC000
#define MEM_ARM_LOCALBUS_ADDR (BASE_ADDRESS_INT_PERI + 1*MEM_SIZE_IN_BYTES) //0xFFFEC100
#define MEM_ARM_LOCAL_BUS_MMU_ADDR (BASE_ADDRESS_INT_PERI + 2*MEM_SIZE_IN_BYTES) //0xFFFEC200
#define MEM_ARM_HSAB_INTERFACE_ADDR (BASE_ADDRESS_INT_PERI + 3*MEM_SIZE_IN_BYTES) //0xFFFEC300
#define MEM_ARM_HSAB_MMU_ADDR (BASE_ADDRESS_INT_PERI + 4*MEM_SIZE_IN_BYTES) //0xFFFEC400
#define MEM_ARM_TIMER_1_ADDR (BASE_ADDRESS_INT_PERI + 5*MEM_SIZE_IN_BYTES)
#define MEM_ARM_TIMER_2_ADDR (BASE_ADDRESS_INT_PERI + 6*MEM_SIZE_IN_BYTES)
#define MEM_ARM_TIMER_3_ADDR (BASE_ADDRESS_INT_PERI + 7*MEM_SIZE_IN_BYTES)
#define MEM_ARM_WDG_TIMER_ADDR (BASE_ADDRESS_INT_PERI + 8*MEM_SIZE_IN_BYTES)
#define MEM_ARM_API_INTERFACE_ADDR (BASE_ADDRESS_INT_PERI + 9*MEM_SIZE_IN_BYTES) //0xFFFEC900
#define MEM_ARM_RHEA_PRIV__ADDR (BASE_ADDRESS_INT_PERI + 10*MEM_SIZE_IN_BYTES)//0xFFFECA00
#define MEM_ARM_INTH_ADDR (BASE_ADDRESS_INT_PERI + 11*MEM_SIZE_IN_BYTES)//0xFFFECB00
#define MEM_ARM_TC_ADDR (BASE_ADDRESS_INT_PERI + 12*MEM_SIZE_IN_BYTES)//0xFFFECC00
#define MEM_ARM_CLKM_ADDR (BASE_ADDRESS_INT_PERI + 14*MEM_SIZE_IN_BYTES)//0xFFFECE00
#define MEM_ARM_DPLL1_ADDR (BASE_ADDRESS_INT_PERI + 15*MEM_SIZE_IN_BYTES)//0xFFFECF00
#define MEM_ARM_DPLL2_ADDR (BASE_ADDRESS_INT_PERI + 16*MEM_SIZE_IN_BYTES)//0xFFFED000
#define MEM_ARM_DPLL3_ADDR (BASE_ADDRESS_INT_PERI + 17*MEM_SIZE_IN_BYTES)//0xFFFED100
#define MEM_ARM_DSP_MMU_ADDR (BASE_ADDRESS_INT_PERI + 18*MEM_SIZE_IN_BYTES)//0xFFFED200
#define MEM_ARM_RHEA_PUB_ADDR (BASE_ADDRESS_INT_PERI + 19*MEM_SIZE_IN_BYTES)//0xFFFED300
#define MEM_ARM_JTAG_ID_CODE_ADDR (BASE_ADDRESS_INT_PERI + 20*MEM_SIZE_IN_BYTES)//0xFFFED400
#define MEM_ARM_DMA_CONTROLLER_ADDR (BASE_ADDRESS_INT_PERI + 24*MEM_SIZE_IN_BYTES)//0xFFFED800
#define DPLL_BASE_ADDR MEM_ARM_DPLL1_ADDR // 0xFFFECF00
//DPLL_DPLL1_CTL_REG
//-------------------
#define DPLL_DPLL1_CTL_REG GetIo16(DPLL_BASE_ADDR+0x00) // 0xFFFECF00
//DPLL1_CTL_REG寄存器的第14位
#define DPLL_DPLL1_CTL_REG_IAI_POS 14
//DPLL1_CTL_REG寄存器的位數
#define DPLL_DPLL1_CTL_REG_IAI_NUMB 1
//DPLL1_CTL_REG寄存器此位的值
#define DPLL_DPLL1_CTL_REG_IAI_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL1_CTL_REG_IOB_POS 13
#define DPLL_DPLL1_CTL_REG_IOB_NUMB 1
#define DPLL_DPLL1_CTL_REG_IOB_RES_VAL 0x1
/* R/W */
#define DPLL_DPLL1_CTL_REG_TEST_POS 12
#define DPLL_DPLL1_CTL_REG_TEST_NUMB 1
#define DPLL_DPLL1_CTL_REG_TEST_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL1_CTL_REG_PLL_MULT_POS 7
#define DPLL_DPLL1_CTL_REG_PLL_MULT_NUMB 5
#define DPLL_DPLL1_CTL_REG_PLL_MULT_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL1_CTL_REG_PLL_DIV_POS 5
#define DPLL_DPLL1_CTL_REG_PLL_DIV_NUMB 2
#define DPLL_DPLL1_CTL_REG_PLL_DIV_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL1_CTL_REG_PLL_ENABLE_POS 4
#define DPLL_DPLL1_CTL_REG_PLL_ENABLE_NUMB 1
#define DPLL_DPLL1_CTL_REG_PLL_ENABLE_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL1_CTL_REG_BYPASS_DIV_POS 2
#define DPLL_DPLL1_CTL_REG_BYPASS_DIV_NUMB 2
#define DPLL_DPLL1_CTL_REG_BYPASS_DIV_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL1_CTL_REG_BREAKLN_POS 1
#define DPLL_DPLL1_CTL_REG_BREAKLN_NUMB 1
#define DPLL_DPLL1_CTL_REG_BREAKLN_RES_VAL 0x0
/* R */
#define DPLL_DPLL1_CTL_REG_LOCK_POS 0
#define DPLL_DPLL1_CTL_REG_LOCK_NUMB 1
#define DPLL_DPLL1_CTL_REG_LOCK_RES_VAL 0x0
/* R */
//DPLL_DPLL2_CTL_REG
//------------------- // 0xFFFED000
#define DPLL_DPLL2_CTL_REG GetIo16(DPLL_BASE_ADDR+0x100)
#define DPLL_DPLL2_CTL_REG_IAI_POS 14
#define DPLL_DPLL2_CTL_REG_IAI_NUMB 1
#define DPLL_DPLL2_CTL_REG_IAI_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_IOB_POS 13
#define DPLL_DPLL2_CTL_REG_IOB_NUMB 1
#define DPLL_DPLL2_CTL_REG_IOB_RES_VAL 0x1
//R/W
#define DPLL_DPLL2_CTL_REG_TEST_POS 12
#define DPLL_DPLL2_CTL_REG_TEST_NUMB 1
#define DPLL_DPLL2_CTL_REG_TEST_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL2_CTL_REG_PLL_MULT_POS 7
#define DPLL_DPLL2_CTL_REG_PLL_MULT_NUMB 5
#define DPLL_DPLL2_CTL_REG_PLL_MULT_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_PLL_DIV_POS 5
#define DPLL_DPLL2_CTL_REG_PLL_DIV_NUMB 2
#define DPLL_DPLL2_CTL_REG_PLL_DIV_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_PLL_ENABLE_POS 4
#define DPLL_DPLL2_CTL_REG_PLL_ENABLE_NUMB 1
#define DPLL_DPLL2_CTL_REG_PLL_ENABLE_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL2_CTL_REG_BYPASS_DIV_POS 2
#define DPLL_DPLL2_CTL_REG_BYPASS_DIV_NUMB 2
#define DPLL_DPLL2_CTL_REG_BYPASS_DIV_RES_VAL 0x0
//R/W
#define DPLL_DPLL2_CTL_REG_BREAKLN_POS 1
#define DPLL_DPLL2_CTL_REG_BREAKLN_NUMB 1
#define DPLL_DPLL2_CTL_REG_BREAKLN_RES_VAL 0x0
//R
#define DPLL_DPLL2_CTL_REG_LOCK_POS 0
#define DPLL_DPLL2_CTL_REG_LOCK_NUMB 1
#define DPLL_DPLL2_CTL_REG_LOCK_RES_VAL 0x0
/* R */
//DPLL_DPLL3_CTL_REG
//------------------- // 0xFFFED100
#define DPLL_DPLL3_CTL_REG GetIo16(DPLL_BASE_ADDR+0x200)
#define DPLL_DPLL3_CTL_REG_IAI_POS 14
#define DPLL_DPLL3_CTL_REG_IAI_NUMB 1
#define DPLL_DPLL3_CTL_REG_IAI_RES_VAL 0x0
//R/W
#define DPLL_DPLL3_CTL_REG_IOB_POS 13
#define DPLL_DPLL3_CTL_REG_IOB_NUMB 1
#define DPLL_DPLL3_CTL_REG_IOB_RES_VAL 0x1
//R/W
#define DPLL_DPLL3_CTL_REG_TEST_POS 12
#define DPLL_DPLL3_CTL_REG_TEST_NUMB 1
#define DPLL_DPLL3_CTL_REG_TEST_RES_VAL 0x0
//R/W
#define DPLL_DPLL3_CTL_REG_PLL_MULT_POS 7
#define DPLL_DPLL3_CTL_REG_PLL_MULT_NUMB 5
#define DPLL_DPLL3_CTL_REG_PLL_MULT_RES_VAL 0x0
//R/W
#define DPLL_DPLL3_CTL_REG_PLL_DIV_POS 5
#define DPLL_DPLL3_CTL_REG_PLL_DIV_NUMB 2
#define DPLL_DPLL3_CTL_REG_PLL_DIV_RES_VAL 0x0
//R/W
#define DPLL_DPLL3_CTL_REG_PLL_ENABLE_POS 4
#define DPLL_DPLL3_CTL_REG_PLL_ENABLE_NUMB 1
#define DPLL_DPLL3_CTL_REG_PLL_ENABLE_RES_VAL 0x0
//R/W
#define DPLL_DPLL3_CTL_REG_BYPASS_DIV_POS 2
#define DPLL_DPLL3_CTL_REG_BYPASS_DIV_NUMB 2
#define DPLL_DPLL3_CTL_REG_BYPASS_DIV_RES_VAL 0x0
/* R/W */
#define DPLL_DPLL3_CTL_REG_BREAKLN_POS 1
#define DPLL_DPLL3_CTL_REG_BREAKLN_NUMB 1
#define DPLL_DPLL3_CTL_REG_BREAKLN_RES_VAL 0x0
/* R */
#define DPLL_DPLL3_CTL_REG_LOCK_POS 0
#define DPLL_DPLL3_CTL_REG_LOCK_NUMB 1
#define DPLL_DPLL3_CTL_REG_LOCK_RES_VAL 0x0
#define CLKRST_BASE_ADDR MEM_ARM_CLKM_ADDR // 0xFFFECE00
//CLKRST_ARM_CKCTL
//------------------- // 0xFFFECE00
#define CLKRST_ARM_CKCTL GetIo16(CLKRST_BASE_ADDR+0x00)
#define CLKRST_ARM_CKCTL_ARM_INTHCK_POS 14
#define CLKRST_ARM_CKCTL_ARM_INTHCK_NUMB 1
#define CLKRST_ARM_CKCTL_ARM_INTHCK_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_EN_DSPCK_POS 13
#define CLKRST_ARM_CKCTL_EN_DSPCK_NUMB 1
#define CLKRST_ARM_CKCTL_EN_DSPCK_RES_VAL 0x1
//R/W
#define CLKRST_ARM_CKCTL_ARM_TIMXO_POS 12
#define CLKRST_ARM_CKCTL_ARM_TIMXO_NUMB 1
#define CLKRST_ARM_CKCTL_ARM_TIMXO_RES_VAL 0x1
//R/W
#define CLKRST_ARM_CKCTL_DSPMMUDIV_POS 10
#define CLKRST_ARM_CKCTL_DSPMMUDIV_NUMB 2
#define CLKRST_ARM_CKCTL_DSPMMUDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_TCDIV_POS 8
#define CLKRST_ARM_CKCTL_TCDIV_NUMB 2
#define CLKRST_ARM_CKCTL_TCDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_DSPDIV_POS 6
#define CLKRST_ARM_CKCTL_DSPDIV_NUMB 2
#define CLKRST_ARM_CKCTL_DSPDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_ARMDIV_POS 4
#define CLKRST_ARM_CKCTL_ARMDIV_NUMB 2
#define CLKRST_ARM_CKCTL_ARMDIV_RES_VAL 0x0
//R/W
#define CLKRST_ARM_CKCTL_LCDDIV_POS 2
#define CLKRST_ARM_CKCTL_LCDDIV_NUMB 2
#define CLKRST_ARM_CKCTL_LCDDIV_RES_VAL 0x0
//RW
#define CLKRST_ARM_CKCTL_PERDIV_POS 0
#define CLKRST_ARM_CKCTL_PERDIV_NUMB 2
#define CLKRST_ARM_CKCTL_PERDIV_RES_VAL 0x0
//RW
//CLKRST_ARM_IDLECT1
//------------------- // 0xFFFECE04
#define CLKRST_ARM_IDLECT1 GetIo16(CLKRST_BASE_ADDR+0x04)
#define CLKRST_ARM_IDLECT1_SETARM_IDLE_POS 11
#define CLKRST_ARM_IDLECT1_SETARM_IDLE_NUMB 1
#define CLKRST_ARM_IDLECT1_SETARM_IDLE_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_WKUP_MODE_POS 10
#define CLKRST_ARM_IDLECT1_WKUP_MODE_NUMB 1
#define CLKRST_ARM_IDLECT1_WKUP_MODE_RES_VAL 0x1
//R/W
#define CLKRST_ARM_IDLECT1_IDLTIM_ARM_POS 9
#define CLKRST_ARM_IDLECT1_IDLTIM_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLTIM_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLAPI_ARM_POS 8
#define CLKRST_ARM_IDLECT1_IDLAPI_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLAPI_ARM_RES_VAL 0X0
//R/W
#define CLKRST_ARM_IDLECT1_IDLDPLL_ARM_POS 7
#define CLKRST_ARM_IDLECT1_IDLDPLL_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLDPLL_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLIF_ARM_POS 6
#define CLKRST_ARM_IDLECT1_IDLIF_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLIF_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLHSAB_ARM_POS 5
#define CLKRST_ARM_IDLECT1_IDLHSAB_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLHSAB_ARM_RES_VAL 0x0
//R/W
#define CLKRST_ARM_IDLECT1_IDLLB_ARM_POS 4
#define CLKRST_ARM_IDLECT1_IDLLB_ARM_NUMB 1
#define CLKRST_ARM_IDLECT1_IDLLB_ARM_RES_VAL 0x0
//R/W
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