.ref platformsetup
    .global     _entry
    .global	    _main
	.global	    cinit
	.global	    __STACK_SIZE
	.global	   __stack
	
    .sect ".vecs"
    
_entry:    
    ;b       reset
    ldr pc, _reset
    ldr pc, _undefined_instruction
    ldr pc, _software_interrupt
    ldr pc, _prefetch_abort
    ldr pc, _data_abort
    ldr pc, _not_used
    ldr pc, _irq
    ldr pc, _fiq

_reset: 		.word reset
_undefined_instruction: .word undefined_instruction
_software_interrupt:    .word software_interrupt
_prefetch_abort:    .word prefetch_abort
_data_abort:        .word data_abort
_not_used:      .word not_used
_irq:           .word irq
_fiq:           .word fiq

    ;.balignl 16,0xdeadbeef

    .global _TestGoodSDRAM
    .global _TestErrorSDRAM

	.sect ".text"
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* setup Memory and board specific bits prior to relocation.
* relocate armboot to ram
* setup stack
*
*************************************************************************


_TEXT_BASE:
    .word   0x20000000      ;TEXT_BASE

    .global _armboot_start
_armboot_start:
    .word _entry


c_stack		    .long    __stack
c_STACK_SIZE  	.long    __STACK_SIZE
c_cinit       	.long    cinit

*
* These are defined in the board-specific linker script.
*
	

	.if $$isdefed("CONFIG_USE_IRQ")
* IRQ stack memory (calculated at run-time)*
    .global IRQ_STACK_START
IRQ_STACK_START:
    .word   0x0badc0de

* IRQ stack memory (calculated at run-time)*
    .global FIQ_STACK_START
FIQ_STACK_START:
    .word 0x0badc0de
    .endif


*
* the actual reset code
*

reset:
*
* set the cpu to SVC32 mode
*
    mrs r0,cpsr
    bic r0,r0,#0x1f
    orr r0,r0,#0xd3 ;設置成特權模式(supervisor)，且使I=0,禁止IRQ中斷;F=0,禁止FIQ中斷;
    msr cpsr,r0

*
* Set up 925T mode
*
    mov r1, #0x81               ; Set ARM925T configuration.
    mcr p15, #0, r1, c15, c1, #0  ; Write ARM925T configuration register.

*
* turn off the watchdog, unlock/diable sequence 16BIT 
*
    mov  r1, #0xF5
    ldr  r0, WDTIM_MODE
    strh r1, [r0]
    mov  r1, #0xA0
    strh r1, [r0]

    
*
* mask all IRQs by setting all bits in the INTMR - default
* 該部分的寄存器默認時為1，所以該部分的賦值程序可不要 32bit
*
    mvn r1, #0
    ldr r0, REG_IHL1_MIR       ;0xfffecb00+0x04
    str r1, [r0]
    
    ldr r0, REG_IHL2_MIR       ;0xfffe0000+0x04
    str r1, [r0]

    
*
* wait for dpll to lock
*
    ldr  r0, CK_DPLL1       ;0xfffecf00 16bit
    mov  r1, #0x10
    strh r1, [r0]           ;進入鎖定模式(LOCK mode),對該寄存器寫了之后進入bypass模式
poll1:
    ldrh r1, [r0]
    ands r1, r1, #0x01
    beq poll1               ;判斷是否進入到bypass模式
    
    
*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*
    ;.if $$isdefed("CONFIG_INIT_CRITICAL")
*
* 在調試時，用RAM引導，在實際產品上，是在FLASH是引導的，該條件只在調試中使用
*
    bl  cpu_init_crit
    ;.endif
    
    ;*-----------s-------------------------------------------
	;* Move here 'cause _sys_setup may use initialized
	;* global variables. Oct 18, 2001 Zhu,Yaozong
	;*------------------------------------------------------
    ;* PERFORM AUTO-INITIALIZATION.  IF CINIT IS -1, THEN
	;* THERE IS NONE
    ;*------------------------------------------------------
    LDR	R0, c_cinit
	CMN	R0, #1
    BLNE    auto_init
    
    
******************************************************************************************
**********   測試程序                                                           **********
**********  SRAM 測試
    .if 0   
    LDR     R1,SRAM_SIZE
    LDR     R2,TEST_CONST
    LDR     R0,SRAM_START_POINT
    nop
    nop
    ADD     R1,R1,R0
    
TESTLOOP1:    
    STR     R2,[R0],#4
    nop
    nop
    CMP     R0,R1
    BNE     TESTLOOP1

    LDR     R0,SRAM_START_POINT
TESTLOOP2:
    LDR     R3,[R0],#4
    nop
    CMP     R3,R2
    BNE     TESTERROR
    CMP     R0,R1
    BNE     TESTLOOP2
    BL      _TestGoodSDRAM
    B       STARTSP
TESTERROR:
    BL      _TestErrorSDRAM
STARTSP:
    .endif

    LDR     SP, c_stack
    LDR     R0, c_STACK_SIZE
	ADD	SP, SP, R0

    BL       _main
 
L1: BL  L1              ;zhui added 
******************************************************************************************
    
    
    .if 0
relocate:               ; relocate U-Boot to RAM   
    adr r0, _entry      ; r0 <- current position of code  
    ldr r1, _TEXT_BASE  ; test if we run from flash or RAM
    cmp     r0, r1      ; don't reloc during debug    
    
    beq     stack_setup

    ldr r2, _armboot_start
    ldr r3, _bss_start
    sub r2, r3, r2  ; r2 <- size of armboot       
    add r2, r0, r2  ; r2 <- source end address    

copy_loop:
    ldmia   r0!, {r3-r10}   ; copy from source address [r0]   
    stmia   r1!, {r3-r10}   ; copy to   target address [r1]   
    cmp r0, r2              ; until source end addreee [r2]   
    ble copy_loop

* Set up the stack                     *
stack_setup:
    ldr r0, _TEXT_BASE              ; upper 128 KiB: relocated uboot  
    sub r0, r0, #CFG_MALLOC_LEN     ; malloc area (0x20000 + 128*1024)=256k
    sub r0, r0, #CFG_GBL_DATA_SIZE  ; bdinfo  128                 
    .if $$isdefed("CONFIG_USE_IRQ")
    sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)    ; 4k+4k  
    .endif
    sub sp, r0, #12                 ; leave 3 words for abort-stack   

clear_bss:
    ldr r0, _bss_start              ; find start of bss segment   
    add r0, r0, #4                  ; start at first byte of bss
    ldr r1, _bss_end                ; stop here                   
    mov     r2, #0x00000000         ; clear

clbss_l:
    str r2, [r0]                ; clear loop... 
    add r0, r0, #4
    cmp r0, r1
    bne clbss_l

    ldr pc, _start_armboot          ;;;C 程序代碼

_start_armboot: .word start_armboot

    .endif

*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************

cpu_init_crit:
*
* flush v4 I/D caches
*
    
    mov r0, #0
    mcr p15, #0, r0, c7, c7, #0   ; flush v3/v4 cache; Flush I- and D-cache
    mcr p15, #0, r0, c8, c7, #0   ; flush v4 TLB ;Flush I + D TLB

*
* disable MMU stuff and caches   協處理器CP15和MMU配置
*
    mrc p15, #0, r0, c1, c0, #0
    bic r0, r0, #0x00002300     ;@ clear bits 13, 9:8 (--V- --RS)V=0中斷向量表在低位 RS=0沒有訪問權限
    bic r0, r0, #0x00000087     ;@ clear bits 7, 2:0 (B--- -CAM) B=0 設置little-endian C=0 禁止cache A=0禁止地址對齊檢查 M=0禁止MMU
    orr r0, r0, #0x00000002     ;@ set bit 2 (A) Align 設置地址對齊檢查功能
    orr r0, r0, #0x00001000     ;@ set bit 12 (I) I-Cache 激活I-Cache
    mcr p15, #0, r0, c1, c0, #0