; THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR
; REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, 
; INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS 
; FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR 
; COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. 
; TI DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET 
; POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY 
; INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR 
; YOUR USE OF THE PROGRAM.
;
; IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, INCIDENTAL, 
; CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY 
; THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED 
; OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT 
; OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM. 
; EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF 
; REMOVAL OR REINSTALLATION, COMPUTER TIME, LABOR COSTS, LOSS 
; OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF 
; USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S 
; AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF 
; YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS 
; (U.S.$500).
;
; Unless otherwise stated, the Program written and copyrighted 
; by Texas Instruments is distributed as "freeware".  You may, 
; only under TI's copyright in the Program, use and modify the 
; Program without any charge or restriction.  You may 
; distribute to third parties, provided that you transfer a 
; copy of this license to the third party and the third party 
; agrees to these terms by its first use of the Program. You 
; must reproduce the copyright notice and any other legend of 
; ownership on each copy or partial copy, of the Program.
;
; You acknowledge and agree that the Program contains 
; copyrighted material, trade secrets and other TI proprietary 
; information and is protected by copyright laws, 
; international copyright treaties, and trade secret laws, as 
; well as other intellectual property laws.  To protect TI's 
; rights in the Program, you agree not to decompile, reverse 
; engineer, disassemble or otherwise translate any object code 
; versions of the Program to a human-readable form.  You agree 
; that in no event will you alter, remove or destroy any 
; copyright notice included in the Program.  TI reserves all 
; rights not specifically granted under this license. Except 
; as specifically provided herein, nothing in this agreement 
; shall be construed as conferring by implication, estoppel, 
; or otherwise, upon you, any license or other right under any 
; TI patents, copyrights or trade secrets.
;
; You may not use the Program in non-TI devices.

************************************************************************
**  File Name:    InitAIC10.asm
**  Part Number:  TLV320AIC10/11EVM-SW-0012
************************************************************************
**  Copyright (c) Texas Instruments, Inc. 2000
************************************************************************
**
**  Release History:
**     Version      Date          Engr          Description
**      1.00     10-11-2000    Wendy X Fang   Original Release
**
************************************************************************
**
**  Function:
**    This routine identifies AIC10 device hardware configuration, by
**    means of a plug-and-playing algorithm (refer to ...);  and
**    initializes AIC10/11 CODECs (master and slave)control registers,
**    correspondingly.
** 
************************************************************************
**  References:
**  	(1) Data Manual: General-Purpose 3V to 5.5V 16bit 22KSPS DSP Codec 
**        - TLV320AIC10
************************************************************************

      .global     _InitAIC10

************************************************************************
** Include Statements
************************************************************************
      .include  MMRegs.h
      .include  InitAIC10.h

************************************************************************
**  Function Code
************************************************************************
     .text
 
_InitAIC10:
      NOP

******* Connect MCBSP to AIC10EVM *******	
      PORTR  DSP_CPLD_CNTL2, 0x0060 ; select the AIC10-EVM
      NOP                           ; for McBSP read DSP_CNTL2 reg
      NOP
      ANDM   0xFF00, 0x0060         ; masking default 
      ORM    0x0003, 0x0060         ; Connect McBSP to 
      PORTW  0x0060, DSP_CPLD_CNTL2 ;     AIC10-EVM board
      NOP
      NOP

******* Put Data to a Default Condition *******
      LD     #InitVari, DP          ; set page pointer to current page
      NOP
      NOP
      ST     #1, AIC10Num           ; set default value of AIC10 number
      ST     #0, MasterOnFlag       ; set no-master on-board
      ST     #0, IdentErrs          ; set no identification errors

************************************************************************
**  AIC10 Hardware Configuration Identification
************************************************************************
      
******* Step1: (Use McBSP0 for Auto-Master-Detecter)
*******      Clear FSCount & Enable McBSP0 Rx only
IdentStart:
      NOP
      ST     #0, FSCount            ; clear FSCount
      STM    SPCR1, McBSP0_SPSA     ; enable McBSP0 Rx
      LDM    McBSP0_SPSD, A         ;   (by setting bit0 of SPCR1)
      OR     #0x0001, A 
      STLM   A, McBSP0_SPSD
      RPT    #4                     ; wait for 2 SCLKs
      NOP

******* Step2&3:
*******      Wait for Rx finished, count FS & check FSCounter max; &
*******      check DR bit0 (master/slave falg)
FSCycle1:                           ; detect the first master primary-frame
      NOP
      CALL   IfRxRDY0               ; check if a Rx from McBSP0 finished

      ADDM   #1, FSCount            ; increase FS counter 
      LD     FSCount, A             ; check if FS counter>16 (max8AICs)
      SUB    #0x0010, A             ;   FSCount - 16
      BC     InitErr1, AGT          ;   to no-master err if FSCount > 16
      NOP
      NOP
      LDM    McBSP0_DRR1, A         ; load Rx data to regA & clr RRDY flag
      AND    #0x0001, A             ; mask out D0: M/S bit to find master:
      BC     FSCycle1, AEQ          ; wait for next RX if
      NOP                           ;   not found 1st master primary frame
      NOP                           ; else ... to cycle2
      
******* Step4:
*******      when the 1st master AIC10 is  detected,
*******      set flag & clear FSCounter    
      NOP
      ST     #0x0001, MasterOnFlag  ; set master on board flag
      ST     #0x0000, FSCount       ; clear frame sync counter

******* Step5:
*******      count AIC10 device number between 2 master FSs
*******      check if there are ant AIC HW errors
FSCycle2:
      NOP
      CALL   IfRxRDY0               ; check if an Rx data ready
      ADDM   #1, FSCount            ; increase FS counter 

      LDM    McBSP0_DRR1, A         ; ld Rx data to regA & clr RRDY flag
      AND    #0x0001, A             ; mask out D0: M/S bit
      BC     FSCycle2, AEQ          ; wait for next RX if
      NOP                           ;   not found 2ns master primary frame
      NOP                           ; else:                 
      LD     FSCount, A             ; store number of AIC10 devices
      STL    A, AIC10Num
      BC     InitErr0, ALEQ         ; limit AIC10Num from 1 to 8
      NOP                           ; (InitErr0: no AIC10 on board; &
      NOP                           ;  InitErr2: more than 8 AIC10s or
      SUB    #0x0008, A             ;            other mulfuctions)
      BC     InitErr2, AGT
      NOP
      NOP

******* Step6:
*******      wait for the next(3rd) FS for master &
*******      check to make sure no multiple masters
FSC3Wait:
      NOP
      LD     FSCount, A             ; decrease FSCount by 1
      SUB    #0x0001, A
      STL    A, FSCount

      BC     FSC4Wait, ALEQ         ; if current cycle finished
      NOP                           ; skip & go to next cycle
      NOP                           ; else:

      CALL   IfRxRDY0               ; wait for Rx from McBSP0 finished
      LDM    McBSP0_DRR1, A         ; ld Rx data to regA & clr RRDY flag
      AND    #0x0001, A             ; mask out D0: M/S bit
      BC     FSC3Wait, AEQ          ; back loop if no multi-master
      NOP                           ; else: to error routine
      NOP

******* Errors
*******
InitErr2:                           ; number of AICs > 8 (not possible)
      NOP                           ; or multi-master or other HW errors
      NOP
      ADDM   #1, IdentErrs          ; set error flag
      LD     IdentErrs, A
      SUB    #1, A
      BC     IdentStart, AEQ
      NOP
      NOP
      B      InitErr2
      NOP
      NOP

InitErr1:                           ; there is no master AIC10 on board
      NOP
      NOP
      ST     #0x0000, MasterOnFlag  ; clear master on board flag
      B      InitErr1
      NOP
      NOP
      
InitErr0:                           ; there is no AIC10 on board
      NOP
      NOP
      ST     #0x0000, MasterOnFlag  ; clear master on board flag
      ST     #0x0000, AIC10Num      ; clear AIC10 number
      B      InitFinish
      NOP
      NOP
      
******* Step7
*******     Enable McBSP TX &
*******     Transfer Dx with 2nd-comm Request for AIC10Num
*******     to duble check no errors
FSC4Wait:
      NOP
      STM    SPCR2, McBSP0_SPSA     ; enable McBSP0 Tx
      LDM    McBSP0_SPSD, A         ; (by setting bit0 at SPCR2)
      OR     #0x0001, A 
      STLM   A, McBSP0_SPSD
      NOP                           ; wait for stablizing
      NOP
      ST     #0x0000, FSCount       ; reset FS counter
      NOP

FSC4Prim:                           ; cycle4 primary
      NOP
      STM    #SECRequ, McBSP0_DXR1  ; set 2nd comm request
      CALL   IfTxRDY0               ; wait for Tx from McBSP0 finished
      CALL   IfRxRDY0               ; also wait for Rx in
      	
      LD     FSCount, A             ; Check if 1st FS (for master AIC)
      BC     FSC4PM, AEQ            ; yes: to FSC4PM
      NOP
      NOP                           ; no: make sure all are slaves
      LDM    McBSP0_DRR1, A         ; ld Rx data to regA & clr RRDY flag
      AND    #0x0001, A             ; mask out D0: M/S bit
      BC     InitErr2, ANEQ         
      NOP
      NOP
	  B      FSC4Prim1
      NOP
      NOP

FSC4PM:                             ; Cycle4, primary & master FS:
      NOP                           ; make sure it is from master --
      LDM    McBSP0_DRR1, A         ; ld Rx data to regA & clr RRDY flag
      AND    #0x0001, A             ; mask out D0: M/S bit
      BC     InitErr2, AEQ
      NOP
      NOP

FSC4Prim1:                          ; check FSCount < AIC10Num
      NOP
      ADDM   #1, FSCount            ; increase FS counter 
      LD     FSCount, A             ; if (FSCount-AIC10Num) < 0
      SUB    AIC10Num, A
      BC     FSC4Prim, ALT          ; yes: next 2nd comm request        
      NOP                           ; no:  contine
      NOP

******* Step8:
*******     Read AIC10 device ID for master AIC10 to double check no err
FSC4Second:
      NOP
      ST     #0, FSCount            ; clear FSCount
      NOP

FSC4Sec1:
      NOP
      LD     FSCount, A             ; check if the master device by
      BC     FSC4SecS, ANEQ         ;     FSCount (= 0?)
      NOP                           ; NO: skip ID check
      NOP                           ; YES: 
      LD     AIC10Num, A            ; get master AIC ID from Ident
      SUB    #1, A                  ; ID = (AIC10Num-1) << 13
      SFTA   A, 13, A
      OR     #ReadCR1, A            ; ID.OR.CR1, request to read master 
      STLM   A, McBSP0_DXR1         ; set to request read master AIC CR1
      CALL   IfTxRDY0               ; wait for Tx from McBSP0 finished      
      CALL   IfRxRDY0               ; also check Rx get a data
      
      LDM    McBSP0_DRR1, A         ; ld Rx data to regA & clr RRDY flag
      AND    #0xE000, A             ; mask out D15~D13: AIC device ID
      SFTA   A, -13, A              ; shft ID to lowest 3 bits
      ADD    #1, A                  ; get AIC device number from ID
                                    ;   AIC10Num = ((DOUT&0xE000)>>13)+1
      SUB    AIC10Num, A            ; check if ID-DeviceNum = identified
      BC     InitErr2, ANEQ         ; no: to errors
      NOP                           ; else:  to next AIC10 device
      NOP
      BD      FSC4Sec2
      NOP
      NOP

FSC4SecS:                           ; 2ndary comm slave frame(s)
      NOP
      STM    #0x0000, McBSP0_DXR1   ; no 2ndary comm requested
      CALL   IfTxRDY0               ; wait for Tx from McBSP0 finished
      CALL   IfRxRDY0               ; also check Rx get a data
      LDM    McBSP0_DRR1, A         ; ld Rx data to regA & clr RRDY flag
      NOP

FSC4Sec2:
      NOP
      ADDM   #1, FSCount            ; increase FS counter 
      LD     FSCount, A             ; if (FSCount-AIC10Num) < 0
      SUB    AIC10Num, A