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************************************************************************
**  File Name:    InitC5402.asm
**  Part Number:  TLV320AIC10/11EVM-SW-0011
************************************************************************
**  Copyright (c) Texas Instruments, Inc. 2000
************************************************************************
**
**  Release History:
**     Version      Date          Engr          Description
**      1.00     10-11-2000    Wendy X Fang   Original Release
**
************************************************************************
**
**  Function:
**    This routine initializes C5402 DSP system and McBSP registers
**    for communication to AIC10/11EVM. 
**
************************************************************************
**  References:
**  	(1) TMS320C54x DSP, CPU and Peripheral (SPRU131)
**	(2) TMS320C54x DSP, Enhanced Peripheral (SPRU302)
************************************************************************

      .global     _InitC5402

************************************************************************
** Include Statements
************************************************************************
      .include	MMRegs.h

************************************************************************
**  C5402 DSP Memory Mapping Register Initialization
************************************************************************

_InitC5402:
      NOP

      LD     #0, DP                 ; reset data-page pointer
      STM    #0, CLKMD              ; software setting of DSP clock
      STM    #0, CLKMD              ; (to divider mode before setting)
*      STM    #0x1007, CLKMD         ; set C5402 DSP clock to 40MHz
      STM   #0x4007, CLKMD          ; set C5402 DSP clock to 100MHz
                                    ; (based on DSK crystal at 20MHz) 
      
******* Configure C5402 System Registers *******
      STM   #0x2000, SWWSR          ; 2 wait cycle for IO space &
                                    ; 0 wait cycle for data&prog spaces 
      STM   #0x0000,BSCR            ; set wait states for bank switch:
                                    ; 64k mem bank, extra 0 cycle between
                                    ; consecutive prog/data read     
      STM   #0x1800,ST0             ; ST0 at default setting
      STM   #0x2900,ST1             ; ST1 at default setting(note:INTX=1)
      STM   #0x00A0,PMST            ; MC mode & OVLY=1, vectors at 0080h

******* Set up Timer Control Registers *******     
      STM   #0x0010, TCR            ; stop on-chip timer0  
      STM   #0x0010, TCR1           ; stop on-chip timer1 
                                    ; Timer0 is used as main loop timer
*      STM   #2499, PRD              ; timer0 rate=CPUCLK/1/(PRD+1)
                                    ;            =40M/2500=16KHz
      STM   #6249, PRD             ;  if CPU at 100M/6250=16KHz                                    

******* Initialize McBSP0 Registers *******
      STM   SPCR1,  McBSP0_SPSA     ; register subaddr of SPCR1
      STM   #4020h, McBSP0_SPSD     ; McBSP0 recv = left-justify
                                    ; RINT generated by frame sync                                    
      STM   SPCR2,  McBSP0_SPSA     ; register subaddr for SPCR2
                                    ; XINT generated by frame sync
      STM   #0020h, McBSP0_SPSD     ; McBSP0 Tx = FREE(clock stops 
                                    ; to run after SW breakpoint)                              

      STM   RCR1,   McBSP0_SPSA     ; register subaddr of RCR1
      STM   #0040h, McBSP0_SPSD     ; recv frame1 Dlength = 16 bits 
      STM   RCR2,   McBSP0_SPSA     ; register subaddr of RCR2
      STM   #0041h, McBSP0_SPSD     ; recv Phase = 1
                                    ; Set frame2 Dlength = 16bits

      STM   XCR1,   McBSP0_SPSA     ; register subaddr of XCR1
      STM   #0040h, McBSP0_SPSD     ; set the same as recv
      STM   XCR2,   McBSP0_SPSA     ; register subaddr of XCR2
      STM   #0041h, McBSP0_SPSD     ; set the same as recv

; Use this code lines if McBSP0 is used as a master
;      STM   SRGR1,  McBSP0_SPSA     ; register subaddr of sample rate
;                                    ; generator register
;      STM   #0001h, McBSP0_SPSD     ; set to default since CLKR/X
;      STM   SRGR2,  McBSP0_SPSA     ; is input.
;      STM   #2000h, McBSP0_SPSD     ; CLKS is derived from CPU clock

      STM   PCR,    McBSP0_SPSA     ; register subaddress of PCR
      STM   #0000h, McBSP0_SPSD     ; clk and frame from external (slave)
                                    ; FS at pulse-mode(00)
                                    
; Use this code lines if McBSP0 is used as a master
;      STM   SPCR2,  McBSP0_SPSA    ; enable sample rate generator 
;      LDM   McBSP0_SPSD, A
;      OR    #0x0040, A
;      STLM  A, McBSP0_SPSD
;      RPT   #5                     ; Wait 2 sample rate Clk for
;      NOP                          ;    SRG to stabilize
	 
******* Initialize McBSP1 Registers *******
      STM   SPCR1,  McBSP1_SPSA     ; register subaddr of SPCR1
      STM   #4000h, McBSP1_SPSD     ; McBSP1 recv = left-justify
                                    ; RINT generated by frame sync
      STM   SPCR2,  McBSP1_SPSA     ; register subaddr for SPCR2
                                    ; XINT generated by frame sync
      STM   #0000h, McBSP1_SPSD     ; McBSP1 Tx = FREE(clock stops 
                                    ; to run after SW breakpoint

      STM   RCR1,   McBSP1_SPSA     ; register subaddr of RCR1
      STM   #0040h, McBSP1_SPSD     ; recv frame1 Dlength = 16 bits 
      STM   RCR2,   McBSP1_SPSA     ; register subaddr of RCR2
      STM   #0041h, McBSP1_SPSD     ; recv Phase = 1
                                    ; ret frame2 Dlength = 16bits

      STM   XCR1,   McBSP1_SPSA     ; register subaddr of XCR1
      STM   #0040h, McBSP1_SPSD     ; set the same as recv
      STM   XCR2,   McBSP1_SPSA     ; register subaddr of XCR2
      STM   #0041h, McBSP1_SPSD     ; set the same as recv

      STM   PCR,    McBSP1_SPSA     ; register subaddress of PCR
      STM   #0000h, McBSP1_SPSD     ; clk and frame from external (slave)
                                    ; FS at pulse-mode(00)

******* Finish DSP Initialization *******
      STM   #0x0000, IMR            ; disable peripheral interrupts
      STM   #0xFFFF, IFR            ; clear the intrupts' flags
        
      RET                           ; return to main
      NOP
      NOP
	
      .end

************************************************************************
**  End of File -- InitC5402.asm
************************************************************************