status =  RTC_FROM4_RS_ECC_CTL_CLR			| RTC_FROM4_RS_ECC_CTL_FD_E;		*rs_ecc_ctl = status;		break;	    case NAND_ECC_READSYN :		status =  0x00;		*rs_ecc_ctl = status;		break;	    case NAND_ECC_WRITE :		status =  RTC_FROM4_RS_ECC_CTL_CLR			| RTC_FROM4_RS_ECC_CTL_GEN			| RTC_FROM4_RS_ECC_CTL_FD_E;		*rs_ecc_ctl = status;		break;	    default:		BUG();		break;	}}/* * rtc_from4_calculate_ecc - hardware specific code to read ECC code * @mtd:	MTD device structure * @dat:	buffer containing the data to generate ECC codes * @ecc_code	ECC codes calculated * * The ECC code is calculated by the FPGA.  All we have to do is read the values * from the FPGA registers. * * Note: We read from the inverted registers, since data is inverted before * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code * */static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code){	volatile unsigned short * rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);	unsigned short value;	int i;	for (i = 0; i < 8; i++) {		value = *rs_eccn;		ecc_code[i] = (unsigned char)value;		rs_eccn++;	}	ecc_code[7] |= 0x0f;	/* set the last four bits (not used) */}/* * rtc_from4_correct_data - hardware specific code to correct data using ECC code * @mtd:	MTD device structure * @buf:	buffer containing the data to generate ECC codes * @ecc1	ECC codes read * @ecc2	ECC codes calculated * * The FPGA tells us fast, if there's an error or not. If no, we go back happy * else we read the ecc results from the fpga and call the rs library to decode * and hopefully correct the error. * */static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2){	int i, j, res;	unsigned short status;	uint16_t par[6], syn[6];	uint8_t ecc[8];        volatile unsigned short *rs_ecc;	status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));	if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {		return 0;	}	/* Read the syndrom pattern from the FPGA and correct the bitorder */	rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);        for (i = 0; i < 8; i++) {                ecc[i] = revbits[(*rs_ecc) & 0xFF];                rs_ecc++;        }	/* convert into 6 10bit syndrome fields */	par[5] = rs_decoder->index_of[(((uint16_t)ecc[0] >> 0) & 0x0ff) |				      (((uint16_t)ecc[1] << 8) & 0x300)];	par[4] = rs_decoder->index_of[(((uint16_t)ecc[1] >> 2) & 0x03f) |				      (((uint16_t)ecc[2] << 6) & 0x3c0)];	par[3] = rs_decoder->index_of[(((uint16_t)ecc[2] >> 4) & 0x00f) |				      (((uint16_t)ecc[3] << 4) & 0x3f0)];	par[2] = rs_decoder->index_of[(((uint16_t)ecc[3] >> 6) & 0x003) |				      (((uint16_t)ecc[4] << 2) & 0x3fc)];	par[1] = rs_decoder->index_of[(((uint16_t)ecc[5] >> 0) & 0x0ff) |				      (((uint16_t)ecc[6] << 8) & 0x300)];	par[0] = (((uint16_t)ecc[6] >> 2) & 0x03f) | (((uint16_t)ecc[7] << 6) & 0x3c0);	/* Convert to computable syndrome */	for (i = 0; i < 6; i++) {		syn[i] = par[0];		for (j = 1; j < 6; j++)			if (par[j] != rs_decoder->nn)				syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];		/* Convert to index form */		syn[i] = rs_decoder->index_of[syn[i]];	}	/* Let the library code do its magic.*/	res = decode_rs8(rs_decoder, (uint8_t *)buf, par, 512, syn, 0, NULL, 0xff, NULL);	if (res > 0) {		DEBUG (MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: "			"ECC corrected %d errors on read\n", res);	}	return res;}/** * rtc_from4_errstat - perform additional error status checks * @mtd:	MTD device structure * @this:	NAND chip structure * @state:	state or the operation * @status:	status code returned from read status * @page:	startpage inside the chip, must be called with (page & this->pagemask) * * Perform additional error status checks on erase and write failures * to determine if errors are correctable.  For this device, correctable * 1-bit errors on erase and write are considered acceptable. * * note: see pages 34..37 of data sheet for details. * */static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page){	int	er_stat=0;	int	rtn, retlen;	size_t	len;	uint8_t *buf;	int	i;	this->cmdfunc (mtd, NAND_CMD_STATUS_CLEAR, -1, -1);        if (state == FL_ERASING) {		for (i=0; i<4; i++) {			if (status & 1<<(i+1)) {				this->cmdfunc (mtd, (NAND_CMD_STATUS_ERROR + i + 1), -1, -1);				rtn = this->read_byte(mtd);				this->cmdfunc (mtd, NAND_CMD_STATUS_RESET, -1, -1);				if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {					er_stat |= 1<<(i+1);	/* err_ecc_not_avail */				}			}		}	} else if (state == FL_WRITING) {		/* single bank write logic */		this->cmdfunc (mtd, NAND_CMD_STATUS_ERROR, -1, -1);		rtn = this->read_byte(mtd);		this->cmdfunc (mtd, NAND_CMD_STATUS_RESET, -1, -1);		if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {			er_stat |= 1<<1;	/* err_ecc_not_avail */		} else {			len = mtd->oobblock;			buf = kmalloc (len, GFP_KERNEL);			if (!buf) {				printk (KERN_ERR "rtc_from4_errstat: Out of memory!\n");				er_stat = 1;			/* if we can't check, assume failed */			} else {				/* recovery read */				/* page read */				rtn = nand_do_read_ecc (mtd, page, len, &retlen, buf, NULL, this->autooob, 1);				if (rtn) {	/* if read failed or > 1-bit error corrected */					er_stat |= 1<<1;	/* ECC read failed */				}				kfree(buf);			}		}	}	rtn = status;	if (er_stat == 0) {				/* if ECC is available   */		rtn = (status & ~NAND_STATUS_FAIL);	/*   clear the error bit */	}	return rtn;}#endif/* * Main initialization routine */int __init rtc_from4_init (void){	struct nand_chip *this;	unsigned short bcr1, bcr2, wcr2;	int i;	/* Allocate memory for MTD device structure and private data */	rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip),				GFP_KERNEL);	if (!rtc_from4_mtd) {		printk ("Unable to allocate Renesas NAND MTD device structure.\n");		return -ENOMEM;	}	/* Get pointer to private data */	this = (struct nand_chip *) (&rtc_from4_mtd[1]);	/* Initialize structures */	memset((char *) rtc_from4_mtd, 0, sizeof(struct mtd_info));	memset((char *) this, 0, sizeof(struct nand_chip));	/* Link the private data with the MTD structure */	rtc_from4_mtd->priv = this;	/* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */	bcr1 = *SH77X9_BCR1 & ~0x0002;	bcr1 |= 0x0002;	*SH77X9_BCR1 = bcr1;	/* set */	bcr2 = *SH77X9_BCR2 & ~0x0c00;	bcr2 |= 0x0800;	*SH77X9_BCR2 = bcr2;	/* set area 5 wait states */	wcr2 = *SH77X9_WCR2 & ~0x1c00;	wcr2 |= 0x1c00;	*SH77X9_WCR2 = wcr2;	/* Set address of NAND IO lines */	this->IO_ADDR_R = rtc_from4_fio_base;	this->IO_ADDR_W = rtc_from4_fio_base;	/* Set address of hardware control function */	this->hwcontrol = rtc_from4_hwcontrol;	/* Set address of chip select function */        this->select_chip = rtc_from4_nand_select_chip;	/* command delay time (in us) */	this->chip_delay = 100;	/* return the status of the Ready/Busy line */	this->dev_ready = rtc_from4_nand_device_ready;#ifdef RTC_FROM4_HWECC	printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");        this->eccmode = NAND_ECC_HW8_512;	this->options |= NAND_HWECC_SYNDROME;	/* return the status of extra status and ECC checks */	this->errstat = rtc_from4_errstat;	/* set the nand_oobinfo to support FPGA H/W error detection */	this->autooob = &rtc_from4_nand_oobinfo;	this->enable_hwecc = rtc_from4_enable_hwecc;	this->calculate_ecc = rtc_from4_calculate_ecc;	this->correct_data = rtc_from4_correct_data;#else	printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");	this->eccmode = NAND_ECC_SOFT;#endif	/* set the bad block tables to support debugging */	this->bbt_td = &rtc_from4_bbt_main_descr;	this->bbt_md = &rtc_from4_bbt_mirror_descr;	/* Scan to find existence of the device */	if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {		kfree(rtc_from4_mtd);		return -ENXIO;	}	/* Perform 'device recovery' for each chip in case there was a power loss. */	for (i=0; i < this->numchips; i++) {		deplete(rtc_from4_mtd, i);	}#if RTC_FROM4_NO_VIRTBLOCKS	/* use a smaller erase block to minimize wasted space when a block is bad */	/* note: this uses eight times as much RAM as using the default and makes */	/*       mounts take four times as long. */	rtc_from4_mtd->flags |= MTD_NO_VIRTBLOCKS;#endif	/* Register the partitions */	add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);#ifdef RTC_FROM4_HWECC	/* We could create the decoder on demand, if memory is a concern.	 * This way we have it handy, if an error happens	 *	 * Symbolsize is 10 (bits)	 * Primitve polynomial is x^10+x^3+1	 * first consecutive root is 0	 * primitve element to generate roots = 1	 * generator polinomial degree = 6	 */	rs_decoder = init_rs(10, 0x409, 0, 1, 6);	if (!rs_decoder) {		printk (KERN_ERR "Could not create a RS decoder\n");		nand_release(rtc_from4_mtd);		kfree(rtc_from4_mtd);		return -ENOMEM;	}#endif	/* Return happy */	return 0;}module_init(rtc_from4_init);/* * Clean up routine */#ifdef MODULEstatic void __exit rtc_from4_cleanup (void){	/* Release resource, unregister partitions */	nand_release(rtc_from4_mtd);	/* Free the MTD device structure */	kfree (rtc_from4_mtd);#ifdef RTC_FROM4_HWECC	/* Free the reed solomon resources */	if (rs_decoder) {		free_rs(rs_decoder);	}#endif}module_exit(rtc_from4_cleanup);#endifMODULE_LICENSE("GPL");MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");