/* * BRIEF MODULE DESCRIPTION * Galileo Evaluation Boards PCI support. * * The general-purpose functions to read/write and configure the GT64120A's * PCI registers (function names start with pci0 or pci1) are either direct * copies of functions written by Galileo Technology, or are modifications * of their functions to work with Linux 2.4 vs Linux 2.2.  These functions * are Copyright - Galileo Technology. * * Other functions are derived from other MIPS PCI implementations, or were * written by RidgeRun, Inc,  Copyright (C) 2000 RidgeRun, Inc. *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com * * Copyright 2001 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net * *  This program is free software; you can redistribute  it and/or modify it *  under  the terms of  the GNU General  Public License as published by the *  Free Software Foundation;  either version 2 of the  License, or (at your *  option) any later version. * *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT, *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * *  You should have received a copy of the  GNU General Public License along *  with this program; if not, write  to the Free Software Foundation, Inc., *  675 Mass Ave, Cambridge, MA 02139, USA. */#include <linux/config.h>#include <linux/types.h>#include <linux/pci.h>#include <linux/kernel.h>#include <linux/slab.h>#include <linux/version.h>#include <asm/pci.h>#include <asm/io.h>#include <asm/gt64120/gt64120.h>#include <linux/init.h>#ifdef CONFIG_PCI#define SELF 0/* * These functions and structures provide the BIOS scan and mapping of the PCI * devices. */#define MAX_PCI_DEVS 10struct pci_device {	u32 slot;	u32 BARtype[6];	u32 BARsize[6];};static void __init scan_and_initialize_pci(void);static u32 __init scan_pci_bus(struct pci_device *pci_devices);static void __init allocate_pci_space(struct pci_device *pci_devices);/* * The functions that actually read and write to the controller. * *  Copied from or modified from Galileo Technology code. */static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device);static void pci0WriteConfigReg(unsigned int offset,			       struct pci_dev *device, unsigned int data);static unsigned int pci1ReadConfigReg(int offset, struct pci_dev *device);static void pci1WriteConfigReg(unsigned int offset,			       struct pci_dev *device, unsigned int data);static void pci0MapIOspace(unsigned int pci0IoBase,			   unsigned int pci0IoLength);static void pci1MapIOspace(unsigned int pci1IoBase,			   unsigned int pci1IoLength);static void pci0MapMemory0space(unsigned int pci0Mem0Base,				unsigned int pci0Mem0Length);static void pci1MapMemory0space(unsigned int pci1Mem0Base,				unsigned int pci1Mem0Length);static void pci0MapMemory1space(unsigned int pci0Mem1Base,				unsigned int pci0Mem1Length);static void pci1MapMemory1space(unsigned int pci1Mem1Base,				unsigned int pci1Mem1Length);static unsigned int pci0GetIOspaceBase(void);static unsigned int pci0GetIOspaceSize(void);static unsigned int pci0GetMemory0Base(void);static unsigned int pci0GetMemory0Size(void);static unsigned int pci0GetMemory1Base(void);static unsigned int pci0GetMemory1Size(void);static unsigned int pci1GetIOspaceBase(void);static unsigned int pci1GetIOspaceSize(void);static unsigned int pci1GetMemory0Base(void);static unsigned int pci1GetMemory0Size(void);static unsigned int pci1GetMemory1Base(void);static unsigned int pci1GetMemory1Size(void);/*  Functions to implement "pci ops"  */static int galileo_pcibios_read_config_word(struct pci_dev *dev,					    int offset, u16 * val);static int galileo_pcibios_read_config_byte(struct pci_dev *dev,					    int offset, u8 * val);static int galileo_pcibios_read_config_dword(struct pci_dev *dev,					     int offset, u32 * val);static int galileo_pcibios_write_config_byte(struct pci_dev *dev,					     int offset, u8 val);static int galileo_pcibios_write_config_word(struct pci_dev *dev,					     int offset, u16 val);static int galileo_pcibios_write_config_dword(struct pci_dev *dev,					      int offset, u32 val);static void galileo_pcibios_set_master(struct pci_dev *dev);/* *  General-purpose PCI functions. *//* * pci0MapIOspace - Maps PCI0 IO space for the master. * Inputs: base and length of pci0Io */static void pci0MapIOspace(unsigned int pci0IoBase,			   unsigned int pci0IoLength){	unsigned int pci0IoTop =	    (unsigned int) (pci0IoBase + pci0IoLength);	if (pci0IoLength == 0)		pci0IoTop++;	pci0IoBase = (unsigned int) (pci0IoBase >> 21);	pci0IoTop = (unsigned int) (((pci0IoTop - 1) & 0x0fffffff) >> 21);	GT_WRITE(GT_PCI0IOLD_OFS, pci0IoBase);	GT_WRITE(GT_PCI0IOHD_OFS, pci0IoTop);}/* * pci1MapIOspace - Maps PCI1 IO space for the master. * Inputs: base and length of pci1Io */static void pci1MapIOspace(unsigned int pci1IoBase,			   unsigned int pci1IoLength){	unsigned int pci1IoTop =	    (unsigned int) (pci1IoBase + pci1IoLength);	if (pci1IoLength == 0)		pci1IoTop++;	pci1IoBase = (unsigned int) (pci1IoBase >> 21);	pci1IoTop = (unsigned int) (((pci1IoTop - 1) & 0x0fffffff) >> 21);	GT_WRITE(GT_PCI1IOLD_OFS, pci1IoBase);	GT_WRITE(GT_PCI1IOHD_OFS, pci1IoTop);}/* * pci0MapMemory0space - Maps PCI0 memory0 space for the master. * Inputs: base and length of pci0Mem0 */static void pci0MapMemory0space(unsigned int pci0Mem0Base,				unsigned int pci0Mem0Length){	unsigned int pci0Mem0Top = pci0Mem0Base + pci0Mem0Length;	if (pci0Mem0Length == 0)		pci0Mem0Top++;	pci0Mem0Base = pci0Mem0Base >> 21;	pci0Mem0Top = ((pci0Mem0Top - 1) & 0x0fffffff) >> 21;	GT_WRITE(GT_PCI0M0LD_OFS, pci0Mem0Base);	GT_WRITE(GT_PCI0M0HD_OFS, pci0Mem0Top);}/* * pci1MapMemory0space - Maps PCI1 memory0 space for the master. * Inputs: base and length of pci1Mem0 */static void pci1MapMemory0space(unsigned int pci1Mem0Base,				unsigned int pci1Mem0Length){	unsigned int pci1Mem0Top = pci1Mem0Base + pci1Mem0Length;	if (pci1Mem0Length == 0)		pci1Mem0Top++;	pci1Mem0Base = pci1Mem0Base >> 21;	pci1Mem0Top = ((pci1Mem0Top - 1) & 0x0fffffff) >> 21;	GT_WRITE(GT_PCI1M0LD_OFS, pci1Mem0Base);	GT_WRITE(GT_PCI1M0HD_OFS, pci1Mem0Top);}/* * pci0MapMemory1space - Maps PCI0 memory1 space for the master. * Inputs: base and length of pci0Mem1 */static void pci0MapMemory1space(unsigned int pci0Mem1Base,				unsigned int pci0Mem1Length){	unsigned int pci0Mem1Top = pci0Mem1Base + pci0Mem1Length;	if (pci0Mem1Length == 0)		pci0Mem1Top++;	pci0Mem1Base = pci0Mem1Base >> 21;	pci0Mem1Top = ((pci0Mem1Top - 1) & 0x0fffffff) >> 21;	GT_WRITE(GT_PCI0M1LD_OFS, pci0Mem1Base);	GT_WRITE(GT_PCI0M1HD_OFS, pci0Mem1Top);}/* * pci1MapMemory1space - Maps PCI1 memory1 space for the master. * Inputs: base and length of pci1Mem1 */static void pci1MapMemory1space(unsigned int pci1Mem1Base,				unsigned int pci1Mem1Length){	unsigned int pci1Mem1Top = pci1Mem1Base + pci1Mem1Length;	if (pci1Mem1Length == 0)		pci1Mem1Top++;	pci1Mem1Base = pci1Mem1Base >> 21;	pci1Mem1Top = ((pci1Mem1Top - 1) & 0x0fffffff) >> 21;	GT_WRITE(GT_PCI1M1LD_OFS, pci1Mem1Base);	GT_WRITE(GT_PCI1M1HD_OFS, pci1Mem1Top);}/* * pci0GetIOspaceBase - Return PCI0 IO Base Address. * Inputs: N/A * Returns: PCI0 IO Base Address. */static unsigned int pci0GetIOspaceBase(void){	unsigned int base;	GT_READ(GT_PCI0IOLD_OFS, &base);	base = base << 21;	return base;}/* * pci0GetIOspaceSize - Return PCI0 IO Bar Size. * Inputs: N/A * Returns: PCI0 IO Bar Size. */static unsigned int pci0GetIOspaceSize(void){	unsigned int top, base, size;	GT_READ(GT_PCI0IOLD_OFS, &base);	base = base << 21;	GT_READ(GT_PCI0IOHD_OFS, &top);	top = (top << 21);	size = ((top - base) & 0xfffffff);	size = size | 0x1fffff;	return (size + 1);}/* * pci0GetMemory0Base - Return PCI0 Memory 0 Base Address. * Inputs: N/A * Returns: PCI0 Memory 0 Base Address. */static unsigned int pci0GetMemory0Base(void){	unsigned int base;	GT_READ(GT_PCI0M0LD_OFS, &base);	base = base << 21;	return base;}/* * pci0GetMemory0Size - Return PCI0 Memory 0 Bar Size. * Inputs: N/A * Returns: PCI0 Memory 0 Bar Size. */static unsigned int pci0GetMemory0Size(void){	unsigned int top, base, size;	GT_READ(GT_PCI0M0LD_OFS, &base);	base = base << 21;	GT_READ(GT_PCI0M0HD_OFS, &top);	top = (top << 21);	size = ((top - base) & 0xfffffff);	size = size | 0x1fffff;	return (size + 1);}/* * pci0GetMemory1Base - Return PCI0 Memory 1 Base Address. * Inputs: N/A * Returns: PCI0 Memory 1 Base Address. */static unsigned int pci0GetMemory1Base(void){	unsigned int base;	GT_READ(GT_PCI0M1LD_OFS, &base);	base = base << 21;	return base;}/* * pci0GetMemory1Size - Return PCI0 Memory 1 Bar Size. * Inputs: N/A * Returns: PCI0 Memory 1 Bar Size. */static unsigned int pci0GetMemory1Size(void){	unsigned int top, base, size;	GT_READ(GT_PCI0M1LD_OFS, &base);	base = base << 21;	GT_READ(GT_PCI0M1HD_OFS, &top);	top = (top << 21);	size = ((top - base) & 0xfffffff);	size = size | 0x1fffff;	return (size + 1);}/* * pci1GetIOspaceBase - Return PCI1 IO Base Address. * Inputs: N/A * Returns: PCI1 IO Base Address. */static unsigned int pci1GetIOspaceBase(void){	unsigned int base;	GT_READ(GT_PCI1IOLD_OFS, &base);	base = base << 21;	return base;}/* * pci1GetIOspaceSize - Return PCI1 IO Bar Size. * Inputs: N/A * Returns: PCI1 IO Bar Size. */static unsigned int pci1GetIOspaceSize(void){	unsigned int top, base, size;	GT_READ(GT_PCI1IOLD_OFS, &base);	base = base << 21;	GT_READ(GT_PCI1IOHD_OFS, &top);	top = (top << 21);	size = ((top - base) & 0xfffffff);	size = size | 0x1fffff;	return (size + 1);}/* * pci1GetMemory0Base - Return PCI1 Memory 0 Base Address. * Inputs: N/A * Returns: PCI1 Memory 0 Base Address. */static unsigned int pci1GetMemory0Base(void){	unsigned int base;	GT_READ(GT_PCI1M0LD_OFS, &base);