/* $Id$ * * This file is subject to the terms and conditions of the GNU General Public * License.  See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. * Copyright (C) 2000 by Colin Ngam */#ifdef BRINGUPint NeedXbridgeSwap = 0;#endif#include <linux/types.h>#include <linux/config.h>#include <linux/slab.h>#include <linux/module.h>#include <asm/sn/sgi.h>#include <asm/sn/addrs.h>#include <asm/sn/arch.h>#include <asm/sn/iograph.h>#include <asm/sn/invent.h>#include <asm/sn/hcl.h>#include <asm/sn/labelcl.h>#include <asm/sn/xtalk/xwidget.h>#include <asm/sn/pci/bridge.h>#include <asm/sn/pci/pciio.h>#include <asm/sn/pci/pcibr.h>#include <asm/sn/pci/pcibr_private.h>#include <asm/sn/pci/pci_defs.h>#include <asm/sn/prio.h>#include <asm/sn/ioerror_handling.h>#include <asm/sn/xtalk/xbow.h>#include <asm/sn/ioc3.h>#include <asm/sn/eeprom.h>#include <asm/sn/sn1/bedrock.h>#include <asm/sn/sn_private.h>#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)#include <asm/sn/sn1/hubio.h>#include <asm/sn/sn1/hubio_next.h>#endif#ifdef __ia64#define rmallocmap atemapalloc#define rmfreemap atemapfree#define rmfree atefree#define rmalloc atealloc#endif#undef PCIBR_ATE_DEBUG#if defined(BRINGUP)#if 0#define DEBUG 1	 /* To avoid lots of bad printk() formats leave off */#endif#define PCI_DEBUG 1#define ATTACH_DEBUG 1#define PCIBR_SOFT_LIST 1#endif#ifndef	LOCAL#define	LOCAL		static#endif/* * Macros related to the Lucent USS 302/312 usb timeout workaround.  It * appears that if the lucent part can get into a retry loop if it sees a * DAC on the bus during a pio read retry.  The loop is broken after about * 1ms, so we need to set up bridges holding this part to allow at least * 1ms for pio. */#define USS302_TIMEOUT_WAR#ifdef USS302_TIMEOUT_WAR#include <asm/sn/io.h>#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802#define USS302_BRIDGE_TIMEOUT_HLD	4#endif#define PCIBR_LLP_CONTROL_WAR#if defined (PCIBR_LLP_CONTROL_WAR)int                     pcibr_llp_control_war_cnt;#endif				/* PCIBR_LLP_CONTROL_WAR */#define	NEWAf(ptr,n,f)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP))#define NEWA(ptr,n)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP))#define DELA(ptr,n)	(kfree(ptr))#define NEWf(ptr,f)	NEWAf(ptr,1,f)#define NEW(ptr)	NEWA(ptr,1)#define DEL(ptr)	DELA(ptr,1)int                     pcibr_devflag = D_MP;#ifdef LATER#define F(s,n)		{ 1l<<(s),-(s), n }struct reg_desc         bridge_int_status_desc[] ={    F(31, "MULTI_ERR"),    F(30, "PMU_ESIZE_EFAULT"),    F(29, "UNEXPECTED_RESP"),    F(28, "BAD_XRESP_PACKET"),    F(27, "BAD_XREQ_PACKET"),    F(26, "RESP_XTALK_ERROR"),    F(25, "REQ_XTALK_ERROR"),    F(24, "INVALID_ADDRESS"),    F(23, "UNSUPPORTED_XOP"),    F(22, "XREQ_FIFO_OFLOW"),    F(21, "LLP_REC_SNERROR"),    F(20, "LLP_REC_CBERROR"),    F(19, "LLP_RCTY"),    F(18, "LLP_TX_RETRY"),    F(17, "LLP_TCTY"),    F(16, "SSRAM_PERR"),    F(15, "PCI_ABORT"),    F(14, "PCI_PARITY"),    F(13, "PCI_SERR"),    F(12, "PCI_PERR"),    F(11, "PCI_MASTER_TOUT"),    F(10, "PCI_RETRY_CNT"),    F(9, "XREAD_REQ_TOUT"),    F(8, "GIO_BENABLE_ERR"),    F(7, "INT7"),    F(6, "INT6"),    F(5, "INT5"),    F(4, "INT4"),    F(3, "INT3"),    F(2, "INT2"),    F(1, "INT1"),    F(0, "INT0"),    {0}};struct reg_values       space_v[] ={    {PCIIO_SPACE_NONE, "none"},    {PCIIO_SPACE_ROM, "ROM"},    {PCIIO_SPACE_IO, "I/O"},    {PCIIO_SPACE_MEM, "MEM"},    {PCIIO_SPACE_MEM32, "MEM(32)"},    {PCIIO_SPACE_MEM64, "MEM(64)"},    {PCIIO_SPACE_CFG, "CFG"},    {PCIIO_SPACE_WIN(0), "WIN(0)"},    {PCIIO_SPACE_WIN(1), "WIN(1)"},    {PCIIO_SPACE_WIN(2), "WIN(2)"},    {PCIIO_SPACE_WIN(3), "WIN(3)"},    {PCIIO_SPACE_WIN(4), "WIN(4)"},    {PCIIO_SPACE_WIN(5), "WIN(5)"},    {PCIIO_SPACE_BAD, "BAD"},    {0}};struct reg_desc         space_desc[] ={    {0xFF, 0, "space", 0, space_v},    {0}};#if DEBUG#define	device_desc	device_bitsLOCAL struct reg_desc   device_bits[] ={    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},    {BRIDGE_DEV_RT, 0, "RT"},    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},    {BRIDGE_DEV_PREF, 0, "PREF"},    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},    {BRIDGE_DEV_COH, 0, "COH"},    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},    {BRIDGE_DEV_GBR, 0, "GBR"},    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},    {0}};#endif	/* DEBUG */#ifdef SUPPORT_PRINTING_R_FORMATLOCAL struct reg_values xio_cmd_pactyp[] ={    {0x0, "RdReq"},    {0x1, "RdResp"},    {0x2, "WrReqWithResp"},    {0x3, "WrResp"},    {0x4, "WrReqNoResp"},    {0x5, "Reserved(5)"},    {0x6, "FetchAndOp"},    {0x7, "Reserved(7)"},    {0x8, "StoreAndOp"},    {0x9, "Reserved(9)"},    {0xa, "Reserved(a)"},    {0xb, "Reserved(b)"},    {0xc, "Reserved(c)"},    {0xd, "Reserved(d)"},    {0xe, "SpecialReq"},    {0xf, "SpecialResp"},    {0}};LOCAL struct reg_desc   xio_cmd_bits[] ={    {WIDGET_DIDN, -28, "DIDN", "%x"},    {WIDGET_SIDN, -24, "SIDN", "%x"},    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},    {WIDGET_TNUM, -15, "TNUM", "%x"},    {WIDGET_COHERENT, 0, "COHERENT"},    {WIDGET_DS, 0, "DS"},    {WIDGET_GBR, 0, "GBR"},    {WIDGET_VBPM, 0, "VBPM"},    {WIDGET_ERROR, 0, "ERROR"},    {WIDGET_BARRIER, 0, "BARRIER"},    {0}};#endif	/* SUPPORT_PRINTING_R_FORMAT */#if PCIBR_FREEZE_TIME || PCIBR_ATE_DEBUGLOCAL struct reg_desc   ate_bits[] ={    {0xFFFF000000000000ull, -48, "RMF", "%x"},    {~(IOPGSIZE - 1) &			/* may trim off some low bits */     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},    {0x0000000000000F00ull, -8, "port", "%x"},    {0x0000000000000010ull, 0, "Barrier"},    {0x0000000000000008ull, 0, "Prefetch"},    {0x0000000000000004ull, 0, "Precise"},    {0x0000000000000002ull, 0, "Coherent"},    {0x0000000000000001ull, 0, "Valid"},    {0}};#endif#if PCIBR_ATE_DEBUGLOCAL struct reg_values ssram_sizes[] ={    {BRIDGE_CTRL_SSRAM_512K, "512k"},    {BRIDGE_CTRL_SSRAM_128K, "128k"},    {BRIDGE_CTRL_SSRAM_64K, "64k"},    {BRIDGE_CTRL_SSRAM_1K, "1k"},    {0}};LOCAL struct reg_desc   control_bits[] ={    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},    {BRIDGE_CTRL_MAX_TRANS_MASK, -4, "MAX_TRANS", "%d"},    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},    {0}};#endif#endif	/* LATER *//* kbrick widgetnum-to-bus layout */int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */        2,                                      /* 0x8          */        1,                                      /* 0x9          */        0, 0,                                   /* 0xa - 0xb    */        5,                                      /* 0xc          */        6,                                      /* 0xd          */        4,                                      /* 0xe          */        3,                                      /* 0xf          */};/* * Additional PIO spaces per slot are * recorded in this structure. */struct pciio_piospace_s {    pciio_piospace_t        next;	/* another space for this device */    char                    free;	/* 1 if free, 0 if in use               */    pciio_space_t           space;	/* Which space is in use                */    iopaddr_t               start;	/* Starting address of the PIO space    */    size_t                  count;	/* size of PIO space                    */};/* Use io spin locks. This ensures that all the PIO writes from a particular * CPU to a particular IO device are synched before the start of the next * set of PIO operations to the same device. */#define pcibr_lock(pcibr_soft)		io_splock(&pcibr_soft->bs_lock)#define pcibr_unlock(pcibr_soft,s)	io_spunlock(&pcibr_soft->bs_lock,s)#if PCIBR_SOFT_LISTtypedef struct pcibr_list_s *pcibr_list_p;struct pcibr_list_s {    pcibr_list_p            bl_next;    pcibr_soft_t            bl_soft;    devfs_handle_t            bl_vhdl;};pcibr_list_p            pcibr_list = 0;#endiftypedef volatile unsigned *cfg_p;typedef volatile bridgereg_t *reg_p;#define	INFO_LBL_PCIBR_ASIC_REV	"_pcibr_asic_rev"#define	PCIBR_D64_BASE_UNSET	(0xFFFFFFFFFFFFFFFF)#define	PCIBR_D32_BASE_UNSET	(0xFFFFFFFF)#define PCIBR_VALID_SLOT(s)	(s < 8)#ifdef SN_XXXextern int      hub_device_flags_set(devfs_handle_t       widget_dev,                                     hub_widget_flags_t flags);#endifextern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);/* * This is the file operation table for the pcibr driver. * As each of the functions are implemented, put the  * appropriate function name below. */struct file_operations pcibr_fops = {        owner:  THIS_MODULE,        llseek: NULL,        read: NULL,        write: NULL,        readdir: NULL,        poll: NULL,        ioctl: NULL,        mmap: NULL,        open: NULL,        flush: NULL,        release: NULL,        fsync: NULL,        fasync: NULL,        lock: NULL,        readv: NULL,        writev: NULL};extern devfs_handle_t hwgraph_root;extern graph_error_t hwgraph_vertex_unref(devfs_handle_t vhdl);extern int cap_able(uint64_t x);extern uint64_t rmalloc(struct map *mp, size_t size);extern void rmfree(struct map *mp, size_t size, uint64_t a);extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);extern long atoi(register char *p);extern void *swap_ptr(void **loc, void *new);extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl);extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr);extern struct map *rmallocmap(uint64_t mapsiz);extern void rmfreemap(struct map *mp);extern int compare_and_swap_ptr(void **location, void *old_ptr, void *new_ptr);extern int io_path_map_widget(devfs_handle_t vertex);/* ===================================================================== *    Function Table of Contents * *      The order of functions in this file has stopped *      making much sense. We might want to take a look *      at it some time and bring back some sanity, or *      perhaps bust this file into smaller chunks. */LOCAL void              do_pcibr_rrb_clear(bridge_t *, int);LOCAL void              do_pcibr_rrb_flush(bridge_t *, int);LOCAL int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);LOCAL int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);LOCAL int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);LOCAL int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);LOCAL void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);int			pcibr_wrb_flush(devfs_handle_t);int                     pcibr_rrb_alloc(devfs_handle_t, int *, int *);int                     pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);int                     pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);void                    pcibr_rrb_flush(devfs_handle_t);LOCAL int               pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);void                    pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);LOCAL void              pcibr_clearwidint(bridge_t *);LOCAL void              pcibr_setwidint(xtalk_intr_t);LOCAL int               pcibr_probe_slot(bridge_t *, cfg_p, unsigned *);void                    pcibr_init(void);int                     pcibr_attach(devfs_handle_t);int			pcibr_detach(devfs_handle_t);int                     pcibr_open(devfs_handle_t *, int, int, cred_t *);int                     pcibr_close(devfs_handle_t, int, int, cred_t *);int                     pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);int                     pcibr_unmap(devfs_handle_t, vhandl_t *);int                     pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);void                    pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);LOCAL int               pcibr_init_ext_ate_ram(bridge_t *);LOCAL int               pcibr_ate_alloc(pcibr_soft_t, int);LOCAL void              pcibr_ate_free(pcibr_soft_t, int, int);LOCAL pcibr_info_t      pcibr_info_get(devfs_handle_t);LOCAL pcibr_info_t      pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);LOCAL void		pcibr_device_info_free(devfs_handle_t, pciio_slot_t);