* Status Register 0 (ST0) Initialization

K_ARP           .set    000b<<13                 ; ARP can be addressed from 000b -111b; reset value
K_TC            .set    1b<<12                   ; TC = 1 at reset
K_C             .set    1b<<11                   ; C = 1 at reset
K_OVA           .set    1b<<10                   ; OVA = 0 at reset, Set OVA
K_OVB           .set    1b<< 9                   ; OVB = 0 at reset, Set OVB
K_DP            .set    000000000b<<0            ; DP is cleared to 0 at reset
K_ST0			.set	K_ARP|K_TC|K_C|K_OVA|K_OVB|K_DP



* Status Register 1 (ST1) Initialization

K_BRAF          .set    0b << 15                 ; BRAF = 0 at reset
K_CPL           .set    0b << 14                 ; CPL = 0 at reset
K_XF            .set    1b << 13                 ; XF = 1 at reset
K_HM            .set    0b << 12                 ; HM = 0 at reset
K_INTM          .set    1b << 11                 ; INTM = 1
K_ST1_RESR      .set    0b << 10                 ; reserved
K_OVM           .set    1b << 9                  ; OVM = 0 at reset
K_SXM           .set    1b << 8                  ; SXM = 1 at reset
K_C16           .set    0b << 07                 ; C16 = 0 at reset
K_FRCT          .set    1b << 06                 ; FRCT = 0 at reset, Set FRCT
K_CMPT          .set    0b << 05                 ; CMPT = 0 at reset
K_ASM           .set    00000b << 00             ; ASM = 0 at reset
K_ST1_HIGH	.set	K_BRAF|K_CPL|K_XF|K_HM|K_INTM|K_ST1_RESR|K_OVM|K_SXM
K_ST1_LOW	.set 	K_C16|K_FRCT|K_CMPT|K_ASM
K_ST1		.set	K_ST1_HIGH|K_ST1_LOW


* Program Memory Status Register (PMST) Initialization

K_IPTR          .set    111111111b << 07         ; 111111111b at reset
K_MP_MC         .set    1b << 06                 ; 1 at reset
K_OVLY          .set    1b << 05                 ; OVLY = 0 at reset
K_AVIS          .set    0b << 04                 ; AVIS = 0 at reset
K_DROM          .set    0b << 03                 ; DROM = 0 at reset
K_CLKOFF        .set    0b << 02                 ; CLKOFF = 0 at reset
K_PMST_RESR     .set    00b << 0                 ; reserved for 548
                                                 ; bit 0 = SMUL saturation on mulitply
                                                 ; bit 1 = SST = saturation on store
K_PMST	        .set	K_IPTR|K_MP_MC|K_OVLY|K_AVIS|K_DROM|K_CLKOFF|K_PMST_RESR



* Software Wait State Register Organization (SWWSR) Initialization

K_SWWSR_IO      .set    2000h                    ; set the I/O space


* Bank Switching Control Register (BSCR) Initialization

K_BNKCMP        .set    0000b << 12              ; bank size = 64K
K_PS_DS		.set	0b << 11
K_BSCR_RESR     .set    000000000b <<2           ; reserved space
K_BH            .set    0b << 1                  ; BH = 0 at reset
K_EXIO          .set    0b << 0                  ; EXIO = 0 at reset
K_BSCR		.set	K_BNKCMP|K_PS_DS|K_BSCR_RESR|K_BH|K_EXIO

**********************************************************************
*時鐘模式寄存器CLKMD
;PLLSTATUS為第0位，PLL工作狀態(tài)位
;PLLNDIV為第1位，時鐘發(fā)生器選擇位
;PLLON/OFF為第2位，PLL通斷位
;PLLCOUNT：3-10位，PLL計數(shù)器
;PLLDIV：11位，PLL除數(shù)
;PLLMUL：12-15位，PLL乘數(shù)
************************************************************
* CLKMD1	CLKMD2		CLKMD3	CLKMD             CLOCK MODE
*								RESET VALUE 
*	0		0			0		E007h			  PLL*15
*	0		0			1		9007h			  PLL*10
*	0		1			0		4007h			  PLL*5
*	1		0			0		1007h			  PLL*2
*	1		1			0		F007h			  PLL*1
*	1		1			0		F007h			  1/2
*	1		0			1		F007h			  1/4
**********************************************************************

*****************寄存器的默認值設(shè)置************************************
K_ST0M			.set   	1800h
K_ST1M			.set    2900h
;IO空間為2個等待周期，數(shù)據(jù)和程序空間為0個等待周期
K_SWWSR_IOM	    .set	7249h
K_BSCRM			.set	0000h
K_PMSTMM		.set    00A0h 

;定時器控制寄存器的設(shè)置
K_TCR0_SOFT	.set 0b<<11 ;軟件調(diào)試控制位--控制定時器的工作狀態(tài)
K_TCR0_FREE .set 0B<<10 ;軟件調(diào)試控制位--控制定時器的工作狀態(tài)
K_TCR0_PSC  .set 1001B<<6;預(yù)標定值  10ns
K_TCR0_TRB  .set 1B<<5   ;定時器重新加載 --是否可以自動重裝載：可以
K_TCR0_TSS  .set 1B<<4   ;定時器停止狀態(tài)
K_TCR0_TDDR .set 1001B<<0 ;定時器分頻系數(shù)
K_TCR0		.set K_TCR0_SOFT|K_TCR0_FREE|K_TCR0_PSC|K_TCR0_TRB|K_TCR0_TSS|K_TCR0_TDDR
*初始化定時器0
*根據(jù)定時長度計算公式：T=T*(1+TDDR)*(1+PRD)
*給定TDDR=9，PRD=79
TIM1		.set  30h
PRD1		.set  31h
TCR1		.set  32h

OUT_FIFO1_PID .set  11h
OUT_FIFO2_PID .set  20h
OUT_FIFO3_PID .set  0a3h
OUT_FIFO4_PID .set  4h
OUT_FIFO5_PID .set  5h
OUT_FIFO6_PID .set  6h