7.4.1源程序
根據(jù)書中的應(yīng)用例子，有關(guān)CAN模塊的代碼可分為兩部分：第一部分為CAN初始化，包括設(shè)置CAN位時(shí)間和初始化郵箱0，這部分位于主程序中；第二部分位于中斷服務(wù)子程序內(nèi)，一旦從CAN總線上成功接收消息，如果消息已經(jīng)更新，該部分負(fù)責(zé)將此消息拷貝到變量FREQ_TRGT中。具體判斷過程為：將舊的FREQ_TRGT的值與接收到的值相減，若不等于0，F(xiàn)REQ_TRGT將進(jìn)行更新。
1．頭文件CAN.h
;CAN Registers.
CANMDER 	.set 7100h 			;CAN Mailbox Direction/Enable register
CANTCR 		.set 7101h 			;CAN Transmission Control Register
CANRCR 		.set 7102h 			;CAN Receive Control Register
CANMCR 		.set 7103h 			;CAN Master Control Register
CANBCR2 		.set 7104h 			;CAN Bit Configuration Register 2
CANBCR1 		.set 7105h 			;CAN Bit Configuration Register 1
CANESR 		.set 7106h 			;CAN Error Status Register
CANGSR 		.set 7107h 			;CAN Global Status Register
CANCEC 		.set 7108h 			;CAN Transmit and Receive Err counters
CANIFR 		.set 7109h 			;CAN Interrupt Flag Registers
CANIMR 		.set 710ah 			;CAN Interrupt Mask Registers
CANLAM0H 	.set 710bh 			;CAN Local Acceptance Mask MBx0/1
CANLAM0L 	.set 710ch 			;CAN Local Acceptance Mask MBx0/1
CANLAM1H 	.set 710dh 			;CAN Local Acceptance Mask MBx2/3
CANLAM1L 	.set 710eh 			;CAN Local Acceptance Mask MBx2/3
;CAN Mailboxes
CANMSGID0L 	.set 7200h 			;CAN Message ID for mailbox 0 (lower 16
;bits)
CANMSGID0H 	.set 7201h 			;CAN Message ID for mailbox 0 (upper 16
;bits)
CANMSGCTRL0 .set 7202h 			;CAN RTR and DLC
CANMBX0A 	.set 7204h 			;CAN 2 of 8 bytes of Mailbox 0
CANMBX0B 	.set 7205h 			;CAN 2 of 8 bytes of Mailbox 0
CANMBX0C 	.set 7206h 			;CAN 2 of 8 bytes of Mailbox 0
CANMBX0D 	.set 7207h 			;CAN 2 of 8 bytes of Mailbox 0
CANMSGID1L 	.set 7208h 			;CAN Message ID for mailbox 1 (lower 16
;bits)
CANMSGID1H 	.set 7209h 			;CAN Message ID for mailbox 1 (upper 16
;bits)
CANMSGCTRL1 .set 720Ah 			;CAN RTR and DLC
CANMBX1A 	.set 720Ch 			;CAN 2 of 8 bytes of Mailbox 1
CANMBX1B 	.set 720Dh 			;CAN 2 of 8 bytes of Mailbox 1
CANMBX1C	.set 720Eh 			;CAN 2 of 8 bytes of Mailbox 1
CANMBX1D 	.set 720Fh 			;CAN 2 of 8 bytes of Mailbox 1
CANMSGID2L 	.set 7210h 			;CAN Message ID for mailbox 2 (lower 16
;bits)
CANMSGID2H 	.set 7211h 			;CAN Message ID for mailbox 2 (upper 16
;bits)
CANMSGCTRL2 .set 7212h 			;CAN RTR and DLC
CANMBX2A 	.set 7214h 			;CAN 2 of 8 bytes of Mailbox 2
CANMBX2B 	.set 7215h 			;CAN 2 of 8 bytes of Mailbox 2
CANMBX2C 	.set 7216h 			;CAN 2 of 8 bytes of Mailbox 2
CANMBX2D 	.set 7217h 			;CAN 2 of 8 bytes of Mailbox 2
CANMSGID3L 	.set 7218h 			;CAN Message ID for mailbox 3 (lower 16
;bits)
CANMSGID3H 	.set 7219h 			;CAN Message ID for mailbox 3 (upper 16
;bits)
CANMSGCTRL3 .set 721Ah 			;CAN RTR and DLC
CANMBX3A 	.set 721Ch 			;CAN 2 of 8 bytes of Mailbox 3
CANMBX3B 	.set 721Dh 			;CAN 2 of 8 bytes of Mailbox 3
CANMBX3C 	.set 721Eh 			;CAN 2 of 8 bytes of Mailbox 3
CANMBX3D 	.set 721Fh			;CAN 2 of 8 bytes of Mailbox 3
CANMSGID4L 	.set 7220h 			;CAN Message ID for mailbox 4 (lower 16
;bits)
CANMSGID4H 	.set 7221h 			;CAN Message ID for mailbox 4 (upper 16
;bits)
CANMSGCTRL4 .set 7222h 			;CAN RTR and DLC
CANMBX4A 	.set 7224h 			;CAN 2 of 8 bytes of Mailbox 4
CANMBX4B 	.set 7225h 			;CAN 2 of 8 bytes of Mailbox 4
CANMBX4C 	.set 7226h 			;CAN 2 of 8 bytes of Mailbox 4
CANMBX4D 	.set 7227h 			;CAN 2 of 8 bytes of Mailbox 4
CANMSGID5L 	.set 7228h 			;CAN Message ID for mailbox 5 (lower 16
;bits)
CANMSGID5H 	.set 7229h 			;CAN Message ID for mailbox 5 (upper 16
;bits)
CANMSGCTRL5 .set 722Ah 			;CAN RTR and DLC
CANMBX5A 	.set 722Ch 			;CAN 2 of 8 bytes of Mailbox 5
CANMBX5B 	.set 722Dh			;CAN 2 of 8 bytes of Mailbox 5
CANMBX5C 	.set 722Eh 			;CAN 2 of 8 bytes of Mailbox 5
CANMBX5D 	.set 722Fh 			;CAN 2 of 8 bytes of Mailbox 5
2．節(jié)點(diǎn)A匯編主程序send_frequence.asm
;File Name: Send_Frequence.asm 
;Description: A voltage is sent to the F2407A EVM, transformed 
;by ADC, scaled between 200 and 400 and store in
;mailbox 3 before to be sent in the CAN bus.
;Debug directives
.def 			GPR0 				;General purpose register
.bss 			GPR0,1
;Peripheral Registers
.include "x24x_app.h"
;Constant definitions
DP_PF1 		.set 	0E0h 		;Page 1 of peripheral file (7000h/80h)
DP_CAN 		.set 	0E2h 		;CAN Registers page (7100h)
DP_CAN2 		.set 	0E4h 		;CAN RAM page (7200h)
;M A C R O – Definitions
KICK_DOG 			.macro 			;Watchdog reset macro
LDP 			#00E0h
SPLK 		#05555h, WDKEY
SPLK 		#0AAAAh, WDKEY
LDP 			#0h
.endm
;Vector address declarations
.global _c_int0
.sect ".vectors"
RSVECT 	B 		_c_int0 			;PM 0 Reset Vector 1
INT1 		B 		PHANTOM 			;PM 2 Int level 1 4
INT2 		B 		PHANTOM 			;PM 4 Int level 2 5
INT3 		B 		PHANTOM 			;PM 6 Int level 3 6
INT4 		B 		PHANTOM 			;PM 8 Int level 4 7
INT5 		B 		PHANTOM 			;PM A Int level 5 8
INT6 		B 		PHANTOM 			;PM Cint level 6 9
RESERVED 	B 		PHANTOM 			;PM E (Analysis Int) 10
SW_INT8 	B 		PHANTOM 			;PM 10 User S/W int -
SW_INT9 	B 		PHANTOM 			;PM 12 User S/W int -
SW_INT10 	B 		PHANTOM 			;PM 14 User S/W int -
SW_INT11 	B 		PHANTOM 			;PM 16 User S/W int -
SW_INT12 	B 		PHANTOM 			;PM 18 User S/W int -
SW_INT13 	B 		PHANTOM 			;PM 1A User S/W int -
SW_INT14 	B 		PHANTOM 			;PM 1C User S/W int -
SW_INT15 	B 		PHANTOM 			;PM 1E User S/W int -
SW_INT16 	B 		PHANTOM 			;PM 20 User S/W int -
TRAP 		B 		PHANTOM 			;PM 22 Trap vector -
NMI 		B 		PHANTOM 			;PM 24 Non maskable Int 3
EMU_TRAP 	B 		PHANTOM 			;PM 26 Emulator Trap 2
SW_INT20 	B 		PHANTOM 			;PM 28 User S/W int -
SW_INT21 	B 		PHANTOM 			;PM 2A User S/W int -
SW_INT22 	B 		PHANTOM 			;PM 2C User S/W int -
SW_INT23 	B 		PHANTOM 			;PM 2E User S/W int -

;M A I N C O D E - starts here
.text
_c_int0
SETC 		INTM 			;Disable interrupts
CLRC 		SXM 				;Clear Sign Extension Mode
CLRC 		OVM 				;Reset Overflow Mode
LDP 			#DP_PF1
LACC 		#006Fh
SACL 		WDCR 			;WD control reg. at 7028h
KICK_DOG
;Configure Wait State Generator
SPLK 		#0,61h
OUT 			61h,0ffffh
;Configure the shared pins
LDPK 		#225
SPLK 		#0FFFFH,OCRA
SPLK 		#0FFF3H,OCRB
;CAN Mailbox Initialization
LDP 			#DP_CAN
SPLK 		#0000000000000000b,CANMDER 	
;disable each mailbox
SPLK 		#0000000100000000b,CANMCR
;bit 8 CDR: Change data field request
LDP 			#DP_CAN2
SPLK 		#1111111111111111b,CANMSGID3H
SPLK 		#1111111111111111b,CANMSGID3L
SPLK 		#0000000000000010b,CANMSGCTRL3
LDP 			#DP_CAN
SPLK 		#0000000000000000b,CANMCR
;bit 8 CDR: Change data field request
SPLK 		#0000000001001000b,CANMDER
;bit 0-5 Enable mailbox 3
;bit 7 0: mailbox 3 configured as a transmit mailbox
;CAN Bit Timing Configuration 
SPLK 		#0001000000000000b,CANMCR
;bit 12 Change configuration register
W_CCE 
BIT 			CANGSR,#0Bh 	;Wait for Change configuration
BCND 		W_CCE,NTC 		;enable
SPLK 		#0000000000000000b,CANBCR2
;bit 0-7 Baud rate prescaler
SPLK 		#0000010101010111b,CANBCR1
;bit 0-2 TSEG1
;bit 3-6 TSEG2
;bit 7 Sample point setting (1: 3 times, 0: once)
;bit 8-A Synchronization jump width
;bit B Synchronization on falling edge
;bit C-F Reserved
SPLK 		#0000010000000000b,CANMCR
;bit 10 1: data Byte order: 0,1 first
;bit 12 0: normal mode
W_NCCE 
BIT 		CANGSR,#0Bh 	;Wait for Change configuration
BCND 		W_NCCE,TC 		;Disable
;Configure ADC Control 2 register
LDP 			#DP_PF1
SPLK 		#0000000000000000b, ADCTRL2
;bit 0-2 000 Prescaler value
;bit 3-4 FIFO2 status
;bit 5 Reserved
;bit 6-7 FIFO1 status
;bit 8 Reserved
;bit 9 0 Mask external SOC input
;bit A 0 Mask EV SOC input
;bit B-F Reserved
;Beginning of the loop
LOOP
SPLK 		#1101000110000001b, ADCTRL1 
;Start ADC conversion
;bit 0 1 Start of conversion
;bit 1-3 000 Channel 0 address
;bit 7 0 End of convert
;bit 8 1 Interrupt flag - write 1 to clear
;bit 9 1 Interrupt mask - enable with 1, mask 0
;bit A 0 Continuous run mode disabled
;bit C 1 Enable ADC1
;bit D 1 Immediate start - 0 = no action
;bit E 1 Free run - ignore suspend
;bit F 1 Soft - Not applicable with bit E = 1
READ_ADC 
LACL 		ADCTRL1 			;wait until end of
AND 			#0000000100000000B 	
;conversion flag
;bit 8 1 Interrupt flag
SUB 			#0000000100000000B
BCND 		READ_ADC, NEQ
;Scale the ADC value
;The result of the conversion has to be scaled between 200 (0 volt)
;and 400 (5 volt)
;Frequence_target = ADC_value/80h + 200
SFR
SFR
SFR
SFR
SFR
SFR
SFR 							;shift 7 times (division by 80h)
ADD 			#200h 			;add 200h
LDP 			#04h
SACL 		GPR0 			;result stored in GPR0
;Store frequency in the mailbox 3
LDP 			#DP_CAN
SPLK 		#0000000000000000b,CANMDER
;bit 0-5 Disable each mailbox
SPLK 		#0000000100000000b,CANMCR
;bit 8 CDR: Change data field request
LDP 			#04h
LACL 		GPR0 			;Load frequency value inside
LDP 			#DP_CAN2 		;the CAN mailbox 3
SACL 		CANMBX3A
LDP 			#DP_CAN
SPLK 		#0000010000000000b,CANMCR
;bit 8 CDR: Change data field request
;bit 10 Data byte order. First sent:0,1
SPLK 		#0000000001001000b,CANMDER
;bit 0-5 Enable mailbox 3
;bit 7 0: mailbox 3 =transmit
;Transmit data to the CAN Bus
SPLK 		#0020h,CANTCR 	;Transmit request for mailbox 3
W_TA 	
BIT 			CANTCR,2 		;Wait for transmission
BCND 		W_TA,NTC 		;acknowledge
W_FLAG 
BIT 			CANIFR,4 		;Wait for interrupt flag
BCND 		W_FLAG,NTC
SPLK 		#2000h,CANTCR 	;Reset TA and flag
B 			LOOP 			;Branch to the beginning of
;the loop.
;MAIN CODE - ends here

;ISR: PHANTOM TYPE: ISR
PHANTOM 	RET 						;return
3．節(jié)點(diǎn)B匯編主程序can_application.asm
;File Name: CAN_application.ASM
;Description: Open loop program. This is an implementation of 3 phase Space
;vector PWM running the F2407A device. External frequency control is
;provided by CAN bus.
;Debug directives
.def 		GPR0 			;General purpose registers.
.def 		GPR1
.def 		GPR2
.def 		ALPHA
.def 		STEP_ANGLE
.def 		FREQ_SETPT
.def 		ENTRY_NEW
.def 		ENTRY_OLD
.def 		dx
.def 		dy
.def 		Ta
.def 		Tb
.def 		Tc
.def 		V
.def 		SPEED_HI
.def 		SPEED_LO
.def 		SPEED_fb
.def 		SPEED_sp
.def 		BCAVG
.def 		PCNT_SETPT
.include x24x_app.h
;Constant Declarations
;Used by the SBIT0 & SBIT1 Macro
B15_MSK 		.set 8000h 		;Bit Mask for 15
B14_MSK 		.set 4000h 		;Bit Mask for 14
B13_MSK 		.set 2000h 		;Bit Mask for 13
B12_MSK 		.set 1000h 		;Bit Mask for 12
B11_MSK 		.set 0800h 		;Bit Mask for 11
B10_MSK 		.set 0400h 		;Bit Mask for 10
B9_MSK 		.set 0200h 		;Bit Mask for 9
B8_MSK 		.set 0100h 		;Bit Mask for 8
B7_MSK 		.set 0080h 		;Bit Mask for 7
B6_MSK 		.set 0040h 		;Bit Mask for 6
B5_MSK 		.set 0020h 		;Bit Mask for 5
B4_MSK 		.set 0010h 		;Bit Mask for 4
B3_MSK 		.set 0008h 		;Bit Mask for 3
B2_MSK 		.set 0004h 		;Bit Mask for 2
B1_MSK 		.set 0002h 		;Bit Mask for 1
B0_MSK 		.set 0001h 		;Bit Mask for 0
WSGR 		.set 0FFFFh
DP_PF1 		.set 0E0h 		;page 1 of peripheral file (7000h/80h)
DP_PF2 		.set 0E1h 		;page 2 of peripheral file (7080h/80h)
DP_PF3 		.set 0E2h 		;page 3 of peripheral file (7100h/80h)
DP_EV 		.set 0E8h 		;EV register data mem page (7400h/80h)
DP_CAN 		.set 0E2h 		;CAN Registers (7100h)
DP_CAN2 		.set 0E4h 		;CAN RAM (7200h)
;Space vector PWM constants
F1 			.set 0256 		;Low Freq point on profile(=15Hz)
F2 			.set 1024 		;High Freq point on profile(=60Hz)
VF_SLOPE 	.set 15291 		;Volts/Hz slope 1.87 in Q13 format
INTERCEPT 	.set 00546 		;Line equation intercept 0.07 in Q13
Vmax 		.set 032767 	;0.99999.. in Q15
Vmin 		.set 09830 		;0.40000.. in Q15
BCNT_MAX 	.set 100 		;100x40uS=0.004 Sec depress to be valid
RMP_DLY_MAX .set 100 		;100x40uS=0.004 sec between steps.
BC_SIZE 		.set 50 			;Box car average size of 50
BC_BUF_STRT .set 300h 		;Start of BC buffer
;Variable Declarations for on chip RAM Block B0
.bss 		GPR0,1 			;General purpose registers.
.bss 		GPR1,1
.bss 		GPR2,1
.bss 		FREQ_SETPT,1 	;Value from 0 --> 255
.bss 		FREQ_TRGT,1 	;Frequency Target value 0 --> 255
.bss 		XF_STATE,1 		;State of XF pin (i.e. a Flag)
.bss 		B1_CNT,1 		;B1 button counter (Inc Freq)
.bss 		B2_CNT,1 		;B2 button counter (Dec Freq)
.bss 		RMP_DLY_CNT,1 	;Ramp rate in adjusting to Target freq.
.bss 		REPRESS_DLY,1 	;Forced delay between Re-presses.
.bss 		S_TABLE,1 		;Data address to store Sine table addr.
.bss 		ALPHA,1
.bss 		STEP_ANGLE,1
.bss 		ENTRY_NEW,1
.bss 		ENTRY_OLD,1
.bss 		SINVAL,1
.bss 		SR_ADDR,1
.bss 		SECTOR_PTR,1
.bss 		SPEED_HI,1
.bss 		SPEED_LO,1
.bss 		SPEED_fb,1
.bss 		SPEED_sp,1
.bss 		BCAVG,1
.bss 		PCNT_SETPT,1
.bss 		dx,1
.bss 		dy,1
.bss 		T,1
.bss 		Ta,1
.bss 		Tb,1
.bss 		Tc,1
.bss 		V,1
.bss 		vf_slope,1
.bss 		FREQ_3BIT,1
.bss 		LED_MASK,1
.bss 		mSEC,1
;M A C R O - Definitions
SBIT0 			.macro			;Clear bit Macro
DMA, 		MASK 		
LACC 		DMA
AND			#(0FFFFh-MASK)
SACL 		DMA
.endm
SBIT1 			.macro			;Set bit Macro
DMA, 		MASK 			
LACC 		DMA
OR 			#MASK
SACL 		DMA
.endm