;*   $Revision: 1.2 $  $Date: 2002/01/07 21:52:15 $ ;**********************************************************************;*		 (C) COPYRIGHT TEXAS INSTRUMENTS, INC. 1996 				  *;*																	  *;*		Interrupt Vector Assignments for 'C54x						  *;**********************************************************************	.title "Interrupt Vectors w/ RTDX for C5XX"	.tab	4	.file	"intvecs.asm"	.mmregs	.ref _c_int00	.ref ATRAP_H;**********************************************************************;*	   Interrupt/TRAP vectors;* ;* Note that not all interupt names will apply to any given target.;* This serves only as a multi-purpose example across the C54x family.;* Consult the TI DSP Reference manual to determine which interrupts ;*   apply to a given target.;**********************************************************************	.sect	".intvecs"RS_V:				; Hardware Reset VectorSINTR_V:			; Software Reset Vector	; Note: no need to push XPC here - reset clears XPC	.if ((__far_mode) & ($isdefed("_BIOSHWINEAR") = 0))	FBD		_c_int00			; Branch to MainLine.	.else	BD		_c_int00			; Branch to MainLine.	.endif	STM		#0100h, SP			; initialize Stack PointerNMI_V:				; Non-maskable interrupt VectorSINT16_V:			; Software Interrupt #16 Vector	B		$	NOP	NOPSINT17_V:			; Software Interrupt #17 Vector	B		$	NOP	NOPSINT18_V:			; Software Interrupt #18 Vector	B		$	NOP	NOPSINT19_V:			; Software Interrupt #19 Vector	B		$	NOP	NOPSINT20_V:			; Software Interrupt #20 Vector	B		$	NOP	NOPSINT21_V:			; Software Interrupt #21 Vector	B		$	NOP	NOPSINT22_V:			; Software Interrupt #22 Vector	B		$	NOP	NOPSINT23_V:			; Software Interrupt #23 Vector	B		$	NOP	NOPSINT24_V:			; Software Interrupt #24 Vector	B		$	NOP	NOPSINT25_V:			; Software Interrupt #25 Vector	B		$	NOP	NOPSINT26_V:			; Software Interrupt #26 Vector	B		$	NOP	NOPSINT27_V:			; Software Interrupt #27 Vector	B		$	NOP	NOPSINT28_V:			; Software Interrupt #28 Vector	B		$	NOP	NOPSINT29_V:			; Software Interrupt #29 Vector (reserved)MTRAP_V:			; Message TRAP Vector	B		$	NOP	NOPSINT30_V:			; Software Interrupt #30 Vector (reserved)ATRAP_V:			; Analysis TRAP Vector	.if ((__far_mode) & ($isdefed("_BIOSHWINEAR") = 0))	; ATRAP ISR MUST Be on same page as RTDX Monitor.	; because this SWI trap can only NEAR return, so storing	; the XPC on the stack would only corrupt it as there is no	; FRET from the ATRAP handler which would pop it off.	;PSHM	XPC					; so do NOT save XPC	FBD		ATRAP_H				; far branch anyway in case ISR mis-located	.else	BD		ATRAP_H 			; Delayed branch to handler	.endif	PSHM	ST0					; save Status before branch	SSBX	CPL 				; switch to stack-based addressingINT0_V:				; External User Interrupt #0 VectorSINT0_V:			; Software Interrupt #0 Vector	B		$	NOP	NOPINT1_V:				; External User Interrupt #1 VectorSINT1_V:			; Software Interrupt #1 Vector	B		$	NOP	NOPINT2_V:				; External User Interrupt #2 VectorSINT2_V:			; Software Interrupt #2 Vector	B		$	NOP	NOPTINT_V:				; Internal Timer Interrupt VectorSINT3_V:			; Software Interrupt #3 Vector	B		$	NOP	NOPRINT0_V:			; Serial Port 0 Receive Interrupt VectorBRINT0_V:			; Buffered Serial Port 0 Receive Interrupt VectorSINT4_V:			; Software Interrupt #4 Vector	B		$	NOP	NOPXINT0_V:			; Serial Port 0 Transmit Interrupt VectorBXINT0_V:			; Buffered Serial Port Transmit Interrupt VectorSINT5_V:			; Software Interrupt #5 Vector	B		$	NOP	NOPRINT1_V:			; Serial Port 1 Receive Interrupt VectorTRINT_V:			; TDM Serial Port Receive InterruptSINT6_V:			; Software Interrupt #6 Vector	B		$	NOP	NOPXINT1_V:			; Serial Port 1 Transmit Interrupt VectorTXINT_V:			; TDM Serial Port Transmit InterruptSINT7_V:			; Software Interrupt #7 Vector	B		$	NOP	NOPINT3_V:				; External User Interrupt #3 VectorSINT8_V:			; Software Interrupt #8 Vector	B		$    	NOP	NOPHPINT_V:			; HPI Interrupt VectorSINT9_V:			; Software Interrupt #9 Vector	B		$	NOP	NOPBRINT1_V:			; Buffered Serial Port 1 Receive Interrupt VectorSINT10_V:			; Software Interrupt #10 Vector	B		$	NOP	NOPBXINT1_V:			; Buffered Serial Port 1 Transmit Interrupt VectorSINT11_V:			; Software Interrupt #11 Vector	B		$	NOP	NOPRESERVED_V:			; Reserved Interrupt Vectors	B		$	NOP	NOP	.end