/* * (C) 2006 Denx * Driver for NAND support, Rick Bronson * borrowed heavily from: * (c) 1999 Machine Vision Holdings, Inc. * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org> * * Added 16-bit nand support * (C) 2004 Texas Instruments */#include <common.h>#include <command.h>#include <malloc.h>#include <asm/io.h>#include <watchdog.h>#ifdef CONFIG_SHOW_BOOT_PROGRESS# include <status_led.h># define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)#else# define SHOW_BOOT_PROGRESS(arg)#endif#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)#include <linux/mtd/nand_legacy.h>#include <linux/mtd/nand_ids.h>#include <jffs2/jffs2.h>#ifdef CONFIG_OMAP1510void archflashwp(void *archdata, int wp);#endif#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))#undef	PSYCHO_DEBUG#undef	NAND_DEBUG/* ****************** WARNING ********************* * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will * erase (or at least attempt to erase) blocks that are marked * bad. This can be very handy if you are _sure_ that the block * is OK, say because you marked a good block bad to test bad * block handling and you are done testing, or if you have * accidentally marked blocks bad. * * Erasing factory marked bad blocks is a _bad_ idea. If the * erase succeeds there is no reliable way to find them again, * and attempting to program or erase bad blocks can affect * the data in _other_ (good) blocks. */#define	 ALLOW_ERASE_BAD_DEBUG 0#define CONFIG_MTD_NAND_ECC  /* enable ECC */#define CONFIG_MTD_NAND_ECC_JFFS2/* bits for nand_legacy_rw() `cmd'; or together as needed */#define NANDRW_READ	0x01#define NANDRW_WRITE	0x00#define NANDRW_JFFS2	0x02#define NANDRW_JFFS2_SKIP	0x04/* * Exported variables etc. *//* Definition of the out of band configuration structure */struct nand_oob_config {	/* position of ECC bytes inside oob */	int ecc_pos[6];	/* position of  bad blk flag inside oob -1 = inactive */	int badblock_pos;	/* position of ECC valid flag inside oob -1 = inactive */	int eccvalid_pos;} oob_config = { {0}, 0, 0};struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};int curr_device = -1; /* Current NAND Device *//* * Exported functionss */int nand_legacy_erase(struct nand_chip* nand, size_t ofs,		     size_t len, int clean);int nand_legacy_rw(struct nand_chip* nand, int cmd,		  size_t start, size_t len,		  size_t * retlen, u_char * buf);void nand_print(struct nand_chip *nand);void nand_print_bad(struct nand_chip *nand);int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,		 size_t * retlen, u_char * buf);int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,		 size_t * retlen, const u_char * buf);/* * Internals */static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,		 size_t * retlen, u_char *buf, u_char *ecc_code);static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,			   size_t * retlen, const u_char * buf,			   u_char * ecc_code);#ifdef CONFIG_MTD_NAND_ECCstatic int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);#endif/* * * Function definitions * *//* returns 0 if block containing pos is OK: *		valid erase block and *		not marked bad, or no bad mark position is specified * returns 1 if marked bad or otherwise invalid */static int check_block (struct nand_chip *nand, unsigned long pos){	size_t retlen;	uint8_t oob_data;	uint16_t oob_data16[6];	int page0 = pos & (-nand->erasesize);	int page1 = page0 + nand->oobblock;	int badpos = oob_config.badblock_pos;	if (pos >= nand->totlen)		return 1;	if (badpos < 0)		return 0;	/* no way to check, assume OK */	if (nand->bus16) {		if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16)		    || (oob_data16[2] & 0xff00) != 0xff00)			return 1;		if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16)		    || (oob_data16[2] & 0xff00) != 0xff00)			return 1;	} else {		/* Note - bad block marker can be on first or second page */		if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data)		    || oob_data != 0xff		    || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data)		    || oob_data != 0xff)			return 1;	}	return 0;}/* print bad blocks in NAND flash */void nand_print_bad(struct nand_chip* nand){	unsigned long pos;	for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {		if (check_block(nand, pos))			printf(" 0x%8.8lx\n", pos);	}	puts("\n");}/* cmd: 0: NANDRW_WRITE			write, fail on bad block *	1: NANDRW_READ			read, fail on bad block *	2: NANDRW_WRITE | NANDRW_JFFS2	write, skip bad blocks *	3: NANDRW_READ | NANDRW_JFFS2	read, data all 0xff for bad blocks *      7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks */int nand_legacy_rw (struct nand_chip* nand, int cmd,		   size_t start, size_t len,		   size_t * retlen, u_char * buf){	int ret = 0, n, total = 0;	char eccbuf[6];	/* eblk (once set) is the start of the erase block containing the	 * data being processed.	 */	unsigned long eblk = ~0;	/* force mismatch on first pass */	unsigned long erasesize = nand->erasesize;	while (len) {		if ((start & (-erasesize)) != eblk) {			/* have crossed into new erase block, deal with			 * it if it is sure marked bad.			 */			eblk = start & (-erasesize); /* start of block */			if (check_block(nand, eblk)) {				if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {					while (len > 0 &&					       start - eblk < erasesize) {						*(buf++) = 0xff;						++start;						++total;						--len;					}					continue;				} else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {					start += erasesize;					continue;				} else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {					/* skip bad block */					start += erasesize;					continue;				} else {					ret = 1;					break;				}			}		}		/* The ECC will not be calculated correctly if		   less than 512 is written or read */		/* Is request at least 512 bytes AND it starts on a proper boundry */		if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))			printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");		if (cmd & NANDRW_READ) {			ret = nand_read_ecc(nand, start,					   min(len, eblk + erasesize - start),					   (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);		} else {			ret = nand_write_ecc(nand, start,					    min(len, eblk + erasesize - start),					    (size_t *)&n, (u_char*)buf, (u_char *)eccbuf);		}		if (ret)			break;		start  += n;		buf   += n;		total += n;		len   -= n;	}	if (retlen)		*retlen = total;	return ret;}void nand_print(struct nand_chip *nand){	if (nand->numchips > 1) {		printf("%s at 0x%lx,\n"		       "\t  %d chips %s, size %d MB, \n"		       "\t  total size %ld MB, sector size %ld kB\n",		       nand->name, nand->IO_ADDR, nand->numchips,		       nand->chips_name, 1 << (nand->chipshift - 20),		       nand->totlen >> 20, nand->erasesize >> 10);	}	else {		printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);		print_size(nand->totlen, ", ");		print_size(nand->erasesize, " sector)\n");	}}/* ------------------------------------------------------------------------- */static int NanD_WaitReady(struct nand_chip *nand, int ale_wait){	/* This is inline, to optimise the common case, where it's ready instantly */	int ret = 0;#ifdef NAND_NO_RB	/* in config file, shorter delays currently wrap accesses */	if(ale_wait)		NAND_WAIT_READY(nand);	/* do the worst case 25us wait */	else		udelay(10);#else	/* has functional r/b signal */	NAND_WAIT_READY(nand);#endif	return ret;}/* NanD_Command: Send a flash command to the flash chip */static inline int NanD_Command(struct nand_chip *nand, unsigned char command){	unsigned long nandptr = nand->IO_ADDR;	/* Assert the CLE (Command Latch Enable) line to the flash chip */	NAND_CTL_SETCLE(nandptr);	/* Send the command */	WRITE_NAND_COMMAND(command, nandptr);	/* Lower the CLE line */	NAND_CTL_CLRCLE(nandptr);#ifdef NAND_NO_RB	if(command == NAND_CMD_RESET){		u_char ret_val;		NanD_Command(nand, NAND_CMD_STATUS);		do {			ret_val = READ_NAND(nandptr);/* wait till ready */		} while((ret_val & 0x40) != 0x40);	}#endif	return NanD_WaitReady(nand, 0);}/* NanD_Address: Set the current address for the flash chip */static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs){	unsigned long nandptr;	int i;	nandptr = nand->IO_ADDR;	/* Assert the ALE (Address Latch Enable) line to the flash chip */	NAND_CTL_SETALE(nandptr);	/* Send the address */	/* Devices with 256-byte page are addressed as:	 * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)	 * there is no device on the market with page256	 * and more than 24 bits.	 * Devices with 512-byte page are addressed as:	 * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)	 * 25-31 is sent only if the chip support it.	 * bit 8 changes the read command to be sent	 * (NAND_CMD_READ0 or NAND_CMD_READ1).	 */	if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)		WRITE_NAND_ADDRESS(ofs, nandptr);	ofs = ofs >> nand->page_shift;	if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) {		for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) {			WRITE_NAND_ADDRESS(ofs, nandptr);		}	}	/* Lower the ALE line */	NAND_CTL_CLRALE(nandptr);	/* Wait for the chip to respond */	return NanD_WaitReady(nand, 1);}/* NanD_SelectChip: Select a given flash chip within the current floor */static inline int NanD_SelectChip(struct nand_chip *nand, int chip){	/* Wait for it to be ready */	return NanD_WaitReady(nand, 0);}/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip){	int mfr, id, i;	NAND_ENABLE_CE(nand);  /* set pin low */	/* Reset the chip */	if (NanD_Command(nand, NAND_CMD_RESET)) {#ifdef NAND_DEBUG		printf("NanD_Command (reset) for %d,%d returned true\n",		       floor, chip);#endif		NAND_DISABLE_CE(nand);  /* set pin high */		return 0;	}	/* Read the NAND chip ID: 1. Send ReadID command */	if (NanD_Command(nand, NAND_CMD_READID)) {#ifdef NAND_DEBUG		printf("NanD_Command (ReadID) for %d,%d returned true\n",		       floor, chip);#endif		NAND_DISABLE_CE(nand);  /* set pin high */		return 0;	}	/* Read the NAND chip ID: 2. Send address byte zero */	NanD_Address(nand, ADDR_COLUMN, 0);	/* Read the manufacturer and device id codes from the device */	mfr = READ_NAND(nand->IO_ADDR);	id = READ_NAND(nand->IO_ADDR);	NAND_DISABLE_CE(nand);  /* set pin high */#ifdef NAND_DEBUG	printf("NanD_Command (ReadID) got %x %x\n", mfr, id);#endif	if (mfr == 0xff || mfr == 0) {		/* No response - return failure */		return 0;	}	/* Check it's the same as the first chip we identified.	 * M-Systems say that any given nand_chip device should only	 * contain _one_ type of flash part, although that's not a	 * hardware restriction. */	if (nand->mfr) {		if (nand->mfr == mfr && nand->id == id) {			return 1;	/* This is another the same the first */		} else {			printf("Flash chip at floor %d, chip %d is different:\n",			       floor, chip);		}	}	/* Print and store the manufacturer and ID codes. */	for (i = 0; nand_flash_ids[i].name != NULL; i++) {		if (mfr == nand_flash_ids[i].manufacture_id &&		    id == nand_flash_ids[i].model_id) {#ifdef NAND_DEBUG			printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "			       "Chip ID: 0x%2.2X (%s)\n", mfr, id,			       nand_flash_ids[i].name);#endif			if (!nand->mfr) {				nand->mfr = mfr;				nand->id = id;				nand->chipshift =				    nand_flash_ids[i].chipshift;				nand->page256 = nand_flash_ids[i].page256;				nand->eccsize = 256;				if (nand->page256) {					nand->oobblock = 256;					nand->oobsize = 8;					nand->page_shift = 8;				} else {					nand->oobblock = 512;					nand->oobsize = 16;					nand->page_shift = 9;				}				nand->pageadrlen = nand_flash_ids[i].pageadrlen;				nand->erasesize  = nand_flash_ids[i].erasesize;				nand->chips_name = nand_flash_ids[i].name;				nand->bus16	 = nand_flash_ids[i].bus16; 				return 1;			}			return 0;		}	}#ifdef NAND_DEBUG	/* We haven't fully identified the chip. Print as much as we know. */	printf("Unknown flash chip found: %2.2X %2.2X\n",	       id, mfr);#endif	return 0;}/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */static void NanD_ScanChips(struct nand_chip *nand){	int floor, chip;	int numchips[NAND_MAX_FLOORS];	int maxchips = NAND_MAX_CHIPS;	int ret = 1;	nand->numchips = 0;	nand->mfr = 0;	nand->id = 0;	/* For each floor, find the number of valid chips it contains */	for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {		ret = 1;		numchips[floor] = 0;		for (chip = 0; chip < maxchips && ret != 0; chip++) {			ret = NanD_IdentChip(nand, floor, chip);			if (ret) {				numchips[floor]++;				nand->numchips++;			}		}	}	/* If there are none at all that we recognise, bail */	if (!nand->numchips) {#ifdef NAND_DEBUG		puts ("No NAND flash chips recognised.\n");#endif		return;	}	/* Allocate an array to hold the information for each chip */	nand->chips = malloc(sizeof(struct Nand) * nand->numchips);	if (!nand->chips) {		puts ("No memory for allocating chip info structures\n");		return;	}	ret = 0;	/* Fill out the chip array with {floor, chipno} for each	 * detected chip in the device. */	for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {		for (chip = 0; chip < numchips[floor]; chip++) {			nand->chips[ret].floor = floor;			nand->chips[ret].chip = chip;			nand->chips[ret].curadr = 0;			nand->chips[ret].curmode = 0x50;			ret++;		}	}	/* Calculate and print the total size of the device */	nand->totlen = nand->numchips * (1 << nand->chipshift);#ifdef NAND_DEBUG	printf("%d flash chips found. Total nand_chip size: %ld MB\n",	       nand->numchips, nand->totlen >> 20);#endif}/* we need to be fast here, 1 us per read translates to 1 second per meg */static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr){	unsigned long nandptr = nand->IO_ADDR;	NanD_Command (nand, NAND_CMD_READ0);	if (nand->bus16) {		u16 val;		while (cntr >= 16) {