#define YSRB    __REG(IMX_DMAC_BASE +0x54)	/* Y-Size Register B */#define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6)	/* Source Address Registers */#define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6)	/* Destination Address Registers */#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6)	/* Count Registers */#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6)	/*燙ontrol Registers */#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6)	/* Request source select Registers */#define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6)	/* Burst length Registers */#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Request timeout Registers */#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6)	/* Bus Utilization Registers *//* TODO: define DMA_REQ lines */#define DCR_DRST           (1<<1)#define DCR_DEN            (1<<0)#define DBTOCR_EN          (1<<15)#define DBTOCR_CNT(x)      ((x) & 0x7fff )#define CNTR_CNT(x)        ((x) & 0xffffff )#define CCR_DMOD_LINEAR    ( 0x0 << 12 )#define CCR_DMOD_2D        ( 0x1 << 12 )#define CCR_DMOD_FIFO      ( 0x2 << 12 )#define CCR_DMOD_EOBFIFO   ( 0x3 << 12 )#define CCR_SMOD_LINEAR    ( 0x0 << 10 )#define CCR_SMOD_2D        ( 0x1 << 10 )#define CCR_SMOD_FIFO      ( 0x2 << 10 )#define CCR_SMOD_EOBFIFO   ( 0x3 << 10 )#define CCR_MDIR_DEC       (1<<9)#define CCR_MSEL_B         (1<<8)#define CCR_DSIZ_32        ( 0x0 << 6 )#define CCR_DSIZ_8         ( 0x1 << 6 )#define CCR_DSIZ_16        ( 0x2 << 6 )#define CCR_SSIZ_32        ( 0x0 << 4 )#define CCR_SSIZ_8         ( 0x1 << 4 )#define CCR_SSIZ_16        ( 0x2 << 4 )#define CCR_REN            (1<<3)#define CCR_RPT            (1<<2)#define CCR_FRC            (1<<1)#define CCR_CEN            (1<<0)#define RTOR_EN            (1<<15)#define RTOR_CLK           (1<<14)#define RTOR_PSC           (1<<13)/* * LCD Controller */#define LCDC_SSA	__REG(IMX_LCDC_BASE+0x00)#define LCDC_SIZE	__REG(IMX_LCDC_BASE+0x04)#define SIZE_XMAX(x)	((((x) >> 4) & 0x3f) << 20)#define SIZE_YMAX(y)    ( (y) & 0x1ff )#define LCDC_VPW	__REG(IMX_LCDC_BASE+0x08)#define VPW_VPW(x)	( (x) & 0x3ff )#define LCDC_CPOS	__REG(IMX_LCDC_BASE+0x0C)#define CPOS_CC1        (1<<31)#define CPOS_CC0        (1<<30)#define CPOS_OP         (1<<28)#define CPOS_CXP(x)     (((x) & 3ff) << 16)#define CPOS_CYP(y)     ((y) & 0x1ff)#define LCDC_LCWHB	__REG(IMX_LCDC_BASE+0x10)#define LCWHB_BK_EN     (1<<31)#define LCWHB_CW(w)     (((w) & 0x1f) << 24)#define LCWHB_CH(h)     (((h) & 0x1f) << 16)#define LCWHB_BD(x)     ((x) & 0xff)#define LCDC_LCHCC	__REG(IMX_LCDC_BASE+0x14)#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)#define LCDC_PCR	__REG(IMX_LCDC_BASE+0x18)#define PCR_TFT         (1<<31)#define PCR_COLOR       (1<<30)#define PCR_PBSIZ_1     (0<<28)#define PCR_PBSIZ_2     (1<<28)#define PCR_PBSIZ_4     (2<<28)#define PCR_PBSIZ_8     (3<<28)#define PCR_BPIX_1      (0<<25)#define PCR_BPIX_2      (1<<25)#define PCR_BPIX_4      (2<<25)#define PCR_BPIX_8      (3<<25)#define PCR_BPIX_12     (4<<25)#define PCR_BPIX_16     (4<<25)#define PCR_PIXPOL      (1<<24)#define PCR_FLMPOL      (1<<23)#define PCR_LPPOL       (1<<22)#define PCR_CLKPOL      (1<<21)#define PCR_OEPOL       (1<<20)#define PCR_SCLKIDLE    (1<<19)#define PCR_END_SEL     (1<<18)#define PCR_END_BYTE_SWAP (1<<17)#define PCR_REV_VS      (1<<16)#define PCR_ACD_SEL     (1<<15)#define PCR_ACD(x)      (((x) & 0x7f) << 8)#define PCR_SCLK_SEL    (1<<7)#define PCR_SHARP       (1<<6)#define PCR_PCD(x)      ((x) & 0x3f)#define LCDC_HCR	__REG(IMX_LCDC_BASE+0x1C)#define HCR_H_WIDTH(x)  (((x) & 0x3f) << 26)#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)#define HCR_H_WAIT_2(x) ((x) & 0xff)#define LCDC_VCR	__REG(IMX_LCDC_BASE+0x20)#define VCR_V_WIDTH(x)  (((x) & 0x3f) << 26)#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)#define VCR_V_WAIT_2(x) ((x) & 0xff)#define LCDC_POS	__REG(IMX_LCDC_BASE+0x24)#define POS_POS(x)      ((x) & 1f)#define LCDC_LSCR1	__REG(IMX_LCDC_BASE+0x28)#define LSCR1_GRAY1(x)  (((x) & 0xf) << 4)#define LSCR1_GRAY2(x)  ((x) & 0xf)#define LCDC_PWMR	__REG(IMX_LCDC_BASE+0x2C)#define PWMR_CLS(x)     (((x) & 0x1ff) << 16)#define PWMR_LDMSK      (1<<15)#define PWMR_SCR1       (1<<10)#define PWMR_SCR0       (1<<9)#define PWMR_CC_EN      (1<<8)#define PWMR_PW(x)      ((x) & 0xff)#define LCDC_DMACR	__REG(IMX_LCDC_BASE+0x30)#define DMACR_BURST     (1<<31)#define DMACR_HM(x)     (((x) & 0xf) << 16)#define DMACR_TM(x)     ((x) &0xf)#define LCDC_RMCR	__REG(IMX_LCDC_BASE+0x34)#define RMCR_LCDC_EN		(1<<1)#define RMCR_SELF_REF		(1<<0)#define LCDC_LCDICR	__REG(IMX_LCDC_BASE+0x38)#define LCDICR_INT_SYN  (1<<2)#define LCDICR_INT_CON  (1)#define LCDC_LCDISR	__REG(IMX_LCDC_BASE+0x40)#define LCDISR_UDR_ERR (1<<3)#define LCDISR_ERR_RES (1<<2)#define LCDISR_EOF     (1<<1)#define LCDISR_BOF     (1<<0)/* *  UART Module */#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12)	/* Receiver Register */#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12)	/* Transmitter Register */#define UCR1(x)  __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12)	/* Control Register 1 */#define UCR2(x)  __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12)	/* Control Register 2 */#define UCR3(x)  __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12)	/* Control Register 3 */#define UCR4(x)  __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12)	/* Control Register 4 */#define UFCR(x)  __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12)	/* FIFO Control Register */#define USR1(x)  __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12)	/* Status Register 1 */#define USR2(x)  __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12)	/* Status Register 2 */#define UESC(x)  __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12)	/* Escape Character Register */#define UTIM(x)  __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12)	/* Escape Timer Register */#define UBIR(x)  __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12)	/* BRM Incremental Register */#define UBMR(x)  __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12)	/* BRM Modulator Register */#define UBRC(x)  __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12)	/* Baud Rate Count Register */#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12)	/* Incremental Preset Register 1 */#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12)	/* Incremental Preset Register 2 */#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12)	/* Incremental Preset Register 3 */#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12)	/* Incremental Preset Register 4 */#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12)	/* BRM Modulator Register 1 */#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12)	/* BRM Modulator Register 2 */#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12)	/* BRM Modulator Register 3 */#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12)	/* BRM Modulator Register 4 */#define UTS(x)   __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12)	/* UART Test Register *//* UART Control Register Bit Fields.*/#define  URXD_CHARRDY    (1<<15)#define  URXD_ERR        (1<<14)#define  URXD_OVRRUN     (1<<13)#define  URXD_FRMERR     (1<<12)#define  URXD_BRK        (1<<11)#define  URXD_PRERR      (1<<10)#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */#define  UCR1_SNDBRK     (1<<4)	 /* Send break */#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */#define  UCR1_DOZE       (1<<1)	 /* Doze */#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */#define  UCR2_ESCI     	 (1<<15) /* Escape seq interrupt enable */#define  UCR2_IRTS  	 (1<<14) /* Ignore RTS pin */#define  UCR2_CTSC  	 (1<<13) /* CTS pin control */#define  UCR2_CTS        (1<<12) /* Clear to send */#define  UCR2_ESCEN      (1<<11) /* Escape enable */#define  UCR2_PREN       (1<<8) /* Parity enable */#define  UCR2_PROE       (1<<7) /* Parity odd/even */#define  UCR2_STPB       (1<<6)	/* Stop */#define  UCR2_WS         (1<<5)	/* Word size */#define  UCR2_RTSEN      (1<<4)	/* Request to send interrupt enable */#define  UCR2_TXEN       (1<<2)	/* Transmitter enabled */#define  UCR2_RXEN       (1<<1)	/* Receiver enabled */#define  UCR2_SRST 	 (1<<0)	/* SW reset */#define  UCR3_DTREN 	 (1<<13) /* DTR interrupt enable */#define  UCR3_PARERREN   (1<<12) /* Parity enable */#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */#define  UCR3_DSR        (1<<10) /* Data set ready */#define  UCR3_DCD        (1<<9)  /* Data carrier detect */#define  UCR3_RI         (1<<8)  /* Ring indicator */#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */#define  UCR3_REF25 	 (1<<3)  /* Ref freq 25 MHz */#define  UCR3_REF30 	 (1<<2)  /* Ref Freq 30 MHz */#define  UCR3_INVT  	 (1<<1)  /* Inverted Infrared transmission */#define  UCR3_BPEN  	 (1<<0)  /* Preset registers enable */#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */#define  UCR4_INVR  	 (1<<9)  /* Inverted infrared reception */#define  UCR4_ENIRI 	 (1<<8)  /* Serial infrared interrupt enable */#define  UCR4_WKEN  	 (1<<7)  /* Wake interrupt enable */#define  UCR4_REF16 	 (1<<6)  /* Ref freq 16 MHz */#define  UCR4_IRSC  	 (1<<5) /* IR special case */#define  UCR4_TCEN  	 (1<<3) /* Transmit complete interrupt enable */#define  UCR4_BKEN  	 (1<<2) /* Break condition interrupt enable */#define  UCR4_OREN  	 (1<<1) /* Receiver overrun interrupt enable */#define  UCR4_DREN  	 (1<<0) /* Recv data ready interrupt enable */#define  UFCR_RXTL_SHF   0      /* Receiver trigger level shift */#define  UFCR_RFDIV      (7<<7) /* Reference freq divider mask */#define  UFCR_TXTL_SHF   10     /* Transmitter trigger level shift */#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */#define  USR1_RTSS  	 (1<<14) /* RTS pin status */#define  USR1_TRDY  	 (1<<13) /* Transmitter ready interrupt/dma flag */#define  USR1_RTSD  	 (1<<12) /* RTS delta */#define  USR1_ESCF  	 (1<<11) /* Escape seq interrupt flag */#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */#define  USR1_RRDY       (1<<9)	/* Receiver ready interrupt/dma flag */#define  USR1_TIMEOUT    (1<<7)	/* Receive timeout interrupt status */#define  USR1_RXDS  	 (1<<6)	/* Receiver idle interrupt flag */#define  USR1_AIRINT	 (1<<5)	/* Async IR wake interrupt flag */#define  USR1_AWAKE 	 (1<<4)	/* Aysnc wake interrupt flag */#define  USR2_ADET  	 (1<<15) /* Auto baud rate detect complete */#define  USR2_TXFE  	 (1<<14) /* Transmit buffer FIFO empty */#define  USR2_DTRF  	 (1<<13) /* DTR edge interrupt flag */#define  USR2_IDLE  	 (1<<12) /* Idle condition */#define  USR2_IRINT 	 (1<<8)	/* Serial infrared interrupt flag */#define  USR2_WAKE  	 (1<<7)	/* Wake */#define  USR2_RTSF  	 (1<<4)	/* RTS edge interrupt flag */#define  USR2_TXDC  	 (1<<3)	/* Transmitter complete */#define  USR2_BRCD  	 (1<<2)	/* Break condition */#define  USR2_ORE        (1<<1)	/* Overrun error */#define  USR2_RDR        (1<<0)	/* Recv data ready */#define  UTS_FRCPERR	 (1<<13) /* Force parity error */#define  UTS_LOOP        (1<<12) /* Loop tx and rx */#define  UTS_TXEMPTY	 (1<<6)	/* TxFIFO empty */#define  UTS_RXEMPTY	 (1<<5)	/* RxFIFO empty */#define  UTS_TXFULL 	 (1<<4)	/* TxFIFO full */#define  UTS_RXFULL 	 (1<<3)	/* RxFIFO full */#define  UTS_SOFTRST	 (1<<0)	/* Software reset *//* General purpose timers registers */#define TCTL1   __REG(IMX_TIM1_BASE)#define TPRER1  __REG(IMX_TIM1_BASE + 0x4)#define TCMP1   __REG(IMX_TIM1_BASE + 0x8)#define TCR1    __REG(IMX_TIM1_BASE + 0xc)#define TCN1    __REG(IMX_TIM1_BASE + 0x10)#define TSTAT1  __REG(IMX_TIM1_BASE + 0x14)#define TCTL2   __REG(IMX_TIM2_BASE)#define TPRER2  __REG(IMX_TIM2_BASE + 0x4)#define TCMP2   __REG(IMX_TIM2_BASE + 0x8)#define TCR2    __REG(IMX_TIM2_BASE + 0xc)#define TCN2    __REG(IMX_TIM2_BASE + 0x10)#define TSTAT2  __REG(IMX_TIM2_BASE + 0x14)/* General purpose timers bitfields */#define TCTL_SWR       (1<<15) /* Software reset */#define TCTL_FRR       (1<<8)  /* Freerun / restart */#define TCTL_CAP       (3<<6)  /* Capture Edge */#define TCTL_OM        (1<<5)  /* output mode */#define TCTL_IRQEN     (1<<4)  /* interrupt enable */#define TCTL_CLKSOURCE (7<<1)  /* Clock source */#define TCTL_TEN       (1)     /* Timer enable */#define TPRER_PRES     (0xff)  /* Prescale */#define TSTAT_CAPT     (1<<1)  /* Capture event */#define TSTAT_COMP     (1)     /* Compare event */#endif				/* _IMX_REGS_H */