/* * IXP PCI Init * (C) Copyright 2004 eslab.whut.edu.cn * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h>#ifdef CONFIG_PCI#include <asm/processor.h>#include <asm/io.h>#include <pci.h>#include <asm/arch/ixp425.h>#include <asm/arch/ixp425pci.h>static void non_prefetch_read (unsigned int addr, unsigned int cmd,			       unsigned int *data);static void non_prefetch_write (unsigned int addr, unsigned int cmd,				unsigned int data);static void configure_pins (void);static void sys_pci_gpio_clock_config (void);static void pci_bus_scan (void);static int pci_device_exists (unsigned int deviceNo);static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,				  unsigned int dev, unsigned int func);static void sys_pci_device_bars_write (void);static void calc_bars (PciBar * Bars[], unsigned int nBars,		       unsigned int startAddr);#define PCI_MEMORY_BUS		0x00000000#define PCI_MEMORY_PHY		0x48000000#define PCI_MEMORY_SIZE		0x04000000#define PCI_MEM_BUS		0x40000000#define PCI_MEM_PHY		0x00000000#define PCI_MEM_SIZE		0x04000000#define	PCI_IO_BUS		0x40000000#define PCI_IO_PHY		0x50000000#define PCI_IO_SIZE		0x10000000struct pci_controller hose;unsigned int nDevices;unsigned int nMBars;unsigned int nIOBars;PciBar *memBars[IXP425_PCI_MAX_BAR];PciBar *ioBars[IXP425_PCI_MAX_BAR];PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val){	unsigned int retval;	unsigned int addr;	/*address bits 31:28 specify the device 10:8 specify the function */	/*Set the address to be read */	addr = BIT ((31 - dev)) | (where & ~3);	non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);	*val = retval;	return (OK);}int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val){	unsigned int n;	unsigned int retval;	unsigned int addr;	unsigned int byteEnables;	n = where % 4;	/*byte enables are 4 bits active low, the position of each	   bit maps to the byte that it enables */	byteEnables =		(~(BIT (n) | BIT ((n + 1)))) &		IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;	byteEnables = byteEnables << PCI_NP_CBE_BESL;	/*address bits 31:28 specify the device 10:8 specify the function */	/*Set the address to be read */	addr = BIT ((31 - dev)) | (where & ~3);	non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);	/*Pick out the word we are interested in */	*val = (retval >> (8 * n));	return (OK);}int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val){	unsigned int retval;	unsigned int n;	unsigned int byteEnables;	unsigned int addr;	n = where % 4;	/*byte enables are 4 bits, active low, the position of each	   bit maps to the byte that it enables */	byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;	byteEnables = byteEnables << PCI_NP_CBE_BESL;	/*address bits 31:28 specify the device, 10:8 specify the function */	/*Set the address to be read */	addr = BIT ((31 - dev)) | (where & ~3);	non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);	/*Pick out the byte we are interested in */	*val = (retval >> (8 * n));	return (OK);}int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val){	unsigned int addr;	unsigned int byteEnables;	unsigned int n;	unsigned int ldata;	n = where % 4;	/*byte enables are 4 bits active low, the position of each	   bit maps to the byte that it enables */	byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;	byteEnables = byteEnables << PCI_NP_CBE_BESL;	ldata = val << (8 * n);	/*address bits 31:28 specify the device 10:8 specify the function */	/*Set the address to be written */	addr = BIT ((31 - dev)) | (where & ~3);	non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);	return (OK);}int pci_write_config_word (pci_dev_t dev, int where, unsigned short val){	unsigned int addr;	unsigned int byteEnables;	unsigned int n;	unsigned int ldata;	n = where % 4;	/*byte enables are 4 bits active low, the position of each	   bit maps to the byte that it enables */	byteEnables =		(~(BIT (n) | BIT ((n + 1)))) &		IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;	byteEnables = byteEnables << PCI_NP_CBE_BESL;	ldata = val << (8 * n);	/*address bits 31:28 specify the device 10:8 specify the function */	/*Set the address to be written */	addr = BIT (31 - dev) | (where & ~3);	non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);	return (OK);}int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val){	unsigned int addr;	/*address bits 31:28 specify the device 10:8 specify the function */	/*Set the address to be written */	addr = BIT (31 - dev) | (where & ~3);	non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);	return (OK);}void non_prefetch_read (unsigned int addr,			unsigned int cmd, unsigned int *data){	REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);	/*set up and execute the read */	REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);	/*The result of the read is now in np_rdata */	REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);	return;}void non_prefetch_write (unsigned int addr,			 unsigned int cmd, unsigned int data){	REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);	/*set up the write */	REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);	/*Execute the write by writing to NP_WDATA */	REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);	return;}/* * PCI controller config registers are accessed through these functions * i.e. these allow us to set up our own BARs etc. */void crp_read (unsigned int offset, unsigned int *data){	REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);	REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);}void crp_write (unsigned int offset, unsigned int data){	/*The CRP address register bit 16 indicates that we want to do a write */	REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,		   PCI_CRP_WRITE | offset);	REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);}/*struct pci_controller *hose*/void pci_ixp_init (struct pci_controller *hose){	unsigned int regval;	hose->first_busno = 0;	hose->last_busno = 0x00;	/* System memory space */	pci_set_region (hose->regions + 0,			PCI_MEMORY_BUS,			PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY);	/* PCI memory space */	pci_set_region (hose->regions + 1,			PCI_MEM_BUS,			PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);	/* PCI I/O space */	pci_set_region (hose->regions + 2,			PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);	hose->region_count = 3;	pci_register_hose (hose);/* ========================================================== 		Init IXP PCI ==========================================================*/	REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);	regval |= 1 << 2;	REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);	configure_pins ();	READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);	WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));	udelay (533);	sys_pci_gpio_clock_config ();	REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);	udelay (100);	READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);	WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));	udelay (533);	crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);	crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);	crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);	crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);	crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);	crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);	/*Setup PCI-AHB and AHB-PCI address mappings */	REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,		   IXP425_PCI_AHBMEMBASE_DEFAULT);