?? disp.lst
字號:
+1 138 ;
+1 139 ;------------------------------------------------------------------------------
+1 140 ;BIT DEFINITIONS
+1 141 ;
+1 142 ; TCON 88H
0088 +1 143 IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE
0089 +1 144 IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
008A +1 145 IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE
008B +1 146 IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
008C +1 147 TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL
008D +1 148 TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG
008E +1 149 TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL
008F +1 150 TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG
+1 151 ;
+1 152 ; SCON0 98H
0098 +1 153 RI BIT SCON0.0 ; RECEIVE INTERRUPT FLAG
0099 +1 154 TI BIT SCON0.1 ; TRANSMIT INTERRUPT FLAG
009A +1 155 RB8 BIT SCON0.2 ; RECEIVE BIT 8
009B +1 156 TB8 BIT SCON0.3 ; TRANSMIT BIT 8
009C +1 157 REN BIT SCON0.4 ; RECEIVE ENABLE
009D +1 158 SM2 BIT SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
009E +1 159 SM1 BIT SCON0.6 ; SERIAL MODE CONTROL BIT 1
009F +1 160 SM0 BIT SCON0.7 ; SERIAL MODE CONTROL BIT 0
+1 161 ;
+1 162 ; IE A8H
00A8 +1 163 EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE
00A9 +1 164 ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE
00AA +1 165 EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE
00AB +1 166 ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE
00AC +1 167 ES BIT IE.4 ; SERIAL PORT INTERRUPT ENABLE
00AD +1 168 ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE
00AF +1 169 EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE
+1 170 ;
+1 171 ; IP B8H
00B8 +1 172 PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY
00B9 +1 173 PT0 BIT IP.1 ; TIMER 0 PRIORITY
00BA +1 174 PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
00BB +1 175 PT1 BIT IP.3 ; TIMER 1 PRIORITY
00BC +1 176 PS BIT IP.4 ; SERIAL PORT PRIORITY
00BD +1 177 PT2 BIT IP.5 ; TIMER 2 PRIORITY
+1 178 ;
+1 179 ; SMB0CN C0H
00C0 +1 180 SMBTOE BIT SMB0CN.0 ; SMBUS 0 TIMEOUT ENABLE
00C1 +1 181 SMBFTE BIT SMB0CN.1 ; SMBUS 0 FREE TIMER ENABLE
00C2 +1 182 AA BIT SMB0CN.2 ; SMBUS 0 ASSERT/ACKNOWLEDGE FLAG
00C3 +1 183 SI BIT SMB0CN.3 ; SMBUS 0 INTERRUPT PENDING FLAG
00C4 +1 184 STO BIT SMB0CN.4 ; SMBUS 0 STOP FLAG
00C5 +1 185 STA BIT SMB0CN.5 ; SMBUS 0 START FLAG
00C6 +1 186 ENSMB BIT SMB0CN.6 ; SMBUS 0 ENABLE
+1 187 ;
+1 188 ; T2CON C8H
00C8 +1 189 CPRL2 BIT T2CON.0 ; CAPTURE OR RELOAD SELECT
00C9 +1 190 CT2 BIT T2CON.1 ; TIMER OR COUNTER SELECT
A51 MACRO ASSEMBLER DISP 07/14/2005 22:06:14 PAGE 4
00CA +1 191 TR2 BIT T2CON.2 ; TIMER 2 ON/OFF CONTROL
00CB +1 192 EXEN2 BIT T2CON.3 ; TIMER 2 EXTERNAL ENABLE FLAG
00CC +1 193 TCLK BIT T2CON.4 ; TRANSMIT CLOCK FLAG
00CD +1 194 RCLK BIT T2CON.5 ; RECEIVE CLOCK FLAG
00CE +1 195 EXF2 BIT T2CON.6 ; EXTERNAL FLAG
00CF +1 196 TF2 BIT T2CON.7 ; TIMER 2 OVERFLOW FLAG
+1 197 ;
+1 198 ; PSW D0H
00D0 +1 199 P BIT PSW.0 ; ACCUMULATOR PARITY FLAG
00D1 +1 200 F1 BIT PSW.1 ; USER FLAG 1
00D2 +1 201 OV BIT PSW.2 ; OVERFLOW FLAG
00D3 +1 202 RS0 BIT PSW.3 ; REGISTER BANK SELECT 0
00D4 +1 203 RS1 BIT PSW.4 ; REGISTER BANK SELECT 1
00D5 +1 204 F0 BIT PSW.5 ; USER FLAG 0
00D6 +1 205 AC BIT PSW.6 ; AUXILIARY CARRY FLAG
00D7 +1 206 CY BIT PSW.7 ; CARRY FLAG
+1 207 ;
+1 208 ; PCA0CN D8H
00D8 +1 209 CCF0 BIT PCA0CN.0 ; PCA 0 MODULE 0 INTERRUPT FLAG
00D9 +1 210 CCF1 BIT PCA0CN.1 ; PCA 0 MODULE 1 INTERRUPT FLAG
00DA +1 211 CCF2 BIT PCA0CN.2 ; PCA 0 MODULE 2 INTERRUPT FLAG
00DB +1 212 CCF3 BIT PCA0CN.3 ; PCA 0 MODULE 3 INTERRUPT FLAG
00DC +1 213 CCF4 BIT PCA0CN.4 ; PCA 0 MODULE 4 INTERRUPT FLAG
00DE +1 214 CR BIT PCA0CN.6 ; PCA 0 COUNTER RUN CONTROL BIT
00DF +1 215 CF BIT PCA0CN.7 ; PCA 0 COUNTER OVERFLOW FLAG
+1 216 ;
+1 217 ; ADC0CN E8H
00E8 +1 218 AD0LJST BIT ADC0CN.0 ; ADC 0 RIGHT JUSTIFY DATA BIT
00E9 +1 219 AD0WINT BIT ADC0CN.1 ; ADC 0 WINDOW COMPARE INTERRUPT FLAG
00EA +1 220 AD0STM0 BIT ADC0CN.2 ; ADC 0 START OF CONVERSION MODE BIT 0
00EB +1 221 AD0STM1 BIT ADC0CN.3 ; ADC 0 START OF CONVERSION MODE BIT 1
00EC +1 222 AD0BUSY BIT ADC0CN.4 ; ADC 0 BUSY FLAG
00ED +1 223 AD0INT BIT ADC0CN.5 ; ADC 0 CONVERISION COMPLETE INTERRUPT FLAG
00EE +1 224 AD0TM BIT ADC0CN.6 ; ADC 0 TRACK MODE
00EF +1 225 AD0EN BIT ADC0CN.7 ; ADC 0 ENABLE
+1 226 ;
+1 227 ; SPI0CN F8H
00F8 +1 228 SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE
00F9 +1 229 MSTEN BIT SPI0CN.1 ; SPI 0 MASTER ENABLE
00FA +1 230 SLVSEL BIT SPI0CN.2 ; SPI 0 SLAVE SELECT
00FB +1 231 TXBSY BIT SPI0CN.3 ; SPI 0 TX BUSY FLAG
00FC +1 232 RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
00FD +1 233 MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG
00FE +1 234 WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
00FF +1 235 SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG
236
007F 237 BIT_COUNT DATA 07FH
007E 238 TIMER DATA 07EH
007D 239 TIMER1 DATA 07DH
007C 240 TEN DATA 07CH
0020 241 DATA_IN DATA 020H
0021 242 DATA_OUT DATA 021H
243
0096 244 CLK BIT P1.6
0097 245 DAT BIT P1.7
0000 246 ORG 0000H
0000 2100 247 JMP START
0100 248 ORG 0100H
0100 75FFDE 249 START: mov WDTCN, #0deh ; disable watchdog timer
0103 75FFAD 250 mov WDTCN, #0adh
0106 75B167 251 mov OSCXCN, #67h ; enable external crystal
252 ; oscillator at 22.1184MHz
253
0109 E4 254 clr A ; wait at least 1ms
010A D5E0FD 255 djnz acc, $ ; wait ~512us
010D D5E0FD 256 djnz acc, $ ; wait ~512us
A51 MACRO ASSEMBLER DISP 07/14/2005 22:06:14 PAGE 5
257
0110 258 osc_wait: ; poll for XTLVLD-->1
0110 E5B1 259 mov a, OSCXCN
0112 30E7FB 260 jnb acc.7, osc_wait
261
0115 43B208 262 orl OSCICN, #08h ; select external oscillator as
263 ; system clock source
0118 43B180 264 orl OSCXCN, #80h ; enable missing clock detector
265
011B 759F80 266 CP1INIT: mov CPT1CN, #080h ; Comparator 1 Control Register
011E 7410 267 mov A, #010h ;CPT1CN
0120 D5E0FD 268 djnz ACC, $ ;CPT1CN wait at least 20us
0123 539FCF 269 anl CPT1CN, #not(30h)
0126 75F640 270 mov EIP1, #040h
0129 757E32 271 MOV TIMER,#50
012C 75E344 272 PORTINIT:mov XBR2, #044h
012F 75A401 273 mov P0MDOUT, #001h
0132 757DFF 274 DELAY0: MOV TIMER1,#255
0135 D57DFD 275 DELAY1: DJNZ TIMER1,DELAY1
0138 D57EF7 276 DJNZ TIMER,DELAY0
013B 538500 277 ANL P5,#00H
013E 7521A4 278 MOV DATA_OUT,#10100100B
0141 317A 279 CALL SEND
0143 78C8 280 MOV R0,#11001000B
0145 7900 281 MOV R1,#00000000B
0147 7F10 282 MOV R7,#16
0149 8821 283 DISPLAY: MOV DATA_OUT,R0 ;在第一個事牘萇舷允?? 快捷鍵說明
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