/*
* File: MVPdma.c
*
* Author: Elliot Hill
*
* Description: This file contains all of the functions used
* for DMA control within the Mobile Videophone (MVP)
* thesis project in the University of Queensland.
*
* Last Modified: 2 October 2001
*/
#include "MVP_dma.h"
/*
* The variables used for the video input DMA.
*/
static volatile uint dma_video_prim_ctrl = 0;
static volatile uint dma_video_sec_ctrl = 0;
static volatile uint dma_video_tcnt = 0;
static volatile uint dma_gcra = 0;
static volatile uint dma_gndxa = 0;
/*
* The variables used for the audio input DMA
*/
static volatile uint dma_audio_prim_ctrl = 0;
static volatile uint dma_audio_sec_ctrl = 0;
static volatile uint dma_audio_tcnt = 0;
/*
* The variables used for the data input DMA
*/
static volatile uint dma_data_prim_ctrl = 0;
static volatile uint dma_data_sec_ctrl = 0;
static volatile uint dma_data_tcnt = 0;
/*
* The variables used for internal data transfer DMA
*/
static volatile uint dma_int_data_prim_ctrl = 0;
static volatile uint dma_int_data_sec_ctrl = 0;
static volatile uint dma_int_data_tcnt = 0;
static volatile uint dma_int_data_src_addr = 0;
static volatile uint dma_int_data_dst_addr = 0;
static volatile uint dma_gcrb = 0;
static volatile uint dma_gndxb = 0;
/*
* Data structures for the holding of data received through the
* serial port
*/
static uint datarecaddr;
static float *datastorage = (float *)DATASTORAGEADDR;
/*
* Global data structures used for the video data address for storage, and the
* audio data address.
*/
uint vid_addr_global;
uint aud_addr_global;
/*
* initialise_DMA() -
*
* This function initialises the DMA for the different sections
* of the MVP.
*/
int initialise_DMA(uint vid_addr0, uint aud_addr)
{
/*
* The first thing needed to be done is to reset the DMA, and disable
* the interrupt system.
*/
dma_reset();
intr_init();
INTR_GLOBAL_DISABLE();
/*
* copy the video and audio addresses over to the global address for each,
* to be used when refreshing.
*/
vid_addr_global = vid_addr0;
aud_addr_global = aud_addr;
/*
* Map the various interrupts generated by the board to
* the CPU.
*/
intr_map(CPU_INT7,ISN_EXT_INT7);
intr_map(CPU_INT8,ISN_DMA_INT0);
intr_map(CPU_INT9,ISN_DMA_INT1);
intr_map(CPU_INT10, ISN_DMA_INT2);
/*
* The interrupts now need to be hooked to the various
* Interrupt Service Routines (ISRs).
*/
intr_hook(start_video_transfer,CPU_INT7);
intr_hook(refresh_video_DMA,CPU_INT8);
intr_hook(refresh_audio_DMA,CPU_INT9);
intr_hook(refresh_and_manip_data_DMA,CPU_INT10);
/*
* Now that our interrupt system is hooked, we can set up the
* DMA for our system.
*
* Video:
* - The source address does not increment after transfer
* - The destination address is loaded from the index
* register. This is due to the need to increment by 32-bits
* after transfer.
* - The TCINT, PRI and RSYNC bits must be set.
*/
LOAD_FIELD(&dma_video_prim_ctrl, DMA_ADDR_NO_MOD, SRC_DIR, SRC_DIR_SZ);
LOAD_FIELD(&dma_video_prim_ctrl, DMA_ADDR_INDX, DST_DIR, DST_DIR_SZ);
LOAD_FIELD(&dma_video_prim_ctrl, SEN_TINT1, RSYNC, RSYNC_SZ);
SET_BIT(&dma_video_prim_ctrl,TCINT);
SET_BIT(&dma_video_prim_ctrl,PRI);
/*
* The only bit of the video dma's secondary register that must
* be set is the block interrupt enable.
*/
SET_BIT(&dma_video_sec_ctrl,BLOCK_IE);
/*
* Setting up the transfer count registers:
*
* Video:
* - 125 lines in the image, with 144 pixels/line (VHDL generated)
*
*/
LOAD_FIELD(&dma_video_tcnt, FRAMES_PER_BLOCK, FRAME_COUNT,
FRAME_COUNT_SZ);
LOAD_FIELD(&dma_video_tcnt, NUM_ELEMENTS, ELEMENT_COUNT,
ELEMENT_COUNT_SZ);
/*
* Setting up the required gcra, gndxa (Video) registers for use
* within the dma_global_init function.
*/
LOAD_FIELD(&dma_gcra, FRAMES_PER_BLOCK, FRAME_COUNT_RELOAD,
FRAME_COUNT_RELOAD_SZ);
LOAD_FIELD(&dma_gcra, NUM_ELEMENTS, ELEMENT_COUNT_RELOAD,
ELEMENT_COUNT_RELOAD_SZ);
LOAD_FIELD(&dma_gndxa, 0x0004, ELEMENT_COUNT_RELOAD,
ELEMENT_COUNT_RELOAD_SZ);
/*
* setup the DMA global init for the video transfer
*/
dma_global_init(
0x0, // aux control reg
dma_gcra, // multiframe video transfers
dma_gcrb, // global count reload B - used in internal transfers.
dma_gndxa, // programmable index for reloading video dst addresses
dma_gndxb, // global index reg B
0x0, // global addr register A - not used
0x0, // global addr register B - not used
0x0, // global addr register C - not used
0x0); // global addr register D - not used
/*
* Audio:
* - The length of a read is 32 bits
* - Destination address is incremented
* - DMA is given priority over CPU
* - RSYNC triggers an interrupts when the McBSP port gets
* data.
* - The Interrupts system for DMA is enabled.
*/
LOAD_FIELD(&dma_audio_prim_ctrl, DMA_ESIZE32, ESIZE, ESIZE_SZ);
LOAD_FIELD(&dma_audio_prim_ctrl, DMA_ADDR_INC, DST_DIR, DST_DIR_SZ);
LOAD_FIELD(&dma_audio_prim_ctrl, DMA_DMA_PRI, PRI, 1);
LOAD_FIELD(&dma_audio_prim_ctrl, SEN_REVT0, RSYNC, RSYNC_SZ);
SET_BIT(&dma_audio_prim_ctrl,TCINT);
/*
* Setting up the Secondary control register for the Audio subsection.
* In this area, we will only need one thing, and that is the ability
* to set and clear the BLOCK_IE (block complete interrupts) so we know
* when to refresh.
*/
SET_BIT(&dma_audio_sec_ctrl, BLOCK_IE);
/*
* Now setting the Transfer count register:
*
* Audio:
* - Element length of 4000 (0.5 seconds worth)
*/
LOAD_FIELD(&dma_audio_tcnt, 1, FRAME_COUNT, FRAME_COUNT_SZ);
LOAD_FIELD(&dma_audio_tcnt, AUD_ELEM_NUM, ELEMENT_COUNT,
ELEMENT_COUNT_SZ);
/*
* Serial Data Transfer Configuration:
* - DMA has priority over CPU
* - Incrementing of Destination address automatically
* - No modification to the source address
* - No DMA interrupts on writing, but trigger one on
* reception
* - 16 bit element size
* - Ability for dma channel to interrupt the CPU
*/
LOAD_FIELD(&dma_data_prim_ctrl, DMA_DMA_PRI, PRI, 1);
LOAD_FIELD(&dma_data_prim_ctrl, DMA_ADDR_NO_MOD, SRC_DIR, SRC_DIR_SZ);
LOAD_FIELD(&dma_data_prim_ctrl, DMA_ADDR_INC, DST_DIR, DST_DIR_SZ);
LOAD_FIELD(&dma_data_prim_ctrl, SEN_REVT0, RSYNC, RSYNC_SZ);
LOAD_FIELD(&dma_data_prim_ctrl, SEN_NONE, WSYNC, WSYNC_SZ);
LOAD_FIELD(&dma_data_prim_ctrl, DMA_ESIZE16, ESIZE, ESIZE_SZ);
SET_BIT(&dma_data_prim_ctrl, TCINT);
// Casting the address of our receive data
datarecaddr = (unsigned int)UARTRECADDR;
/*
* Secondary control register setup for Serial data
*/
SET_BIT(&dma_data_sec_ctrl, BLOCK_IE);
/*
* Serial Data transfer counter setup
*/
LOAD_FIELD(&dma_data_tcnt, 1, FRAME_COUNT, FRAME_COUNT_SZ);
LOAD_FIELD(&dma_data_tcnt, DATA_ELEM_NUM, ELEMENT_COUNT,
ELEMENT_COUNT_SZ);
/*
* Program the auxiliary control register.
*/
SET_BIT(DMA_AUXCR_ADDR,AUXPRI);
/*
* Initialising the DMA video channel with the registers
* altered above.
*/
dma_init(
VIDEO_DMA, // DMA Channel 0
dma_video_prim_ctrl, // Primary control register
dma_video_sec_ctrl, // Secondary control register
DMA_VIDEO_SRC_ADDR, // defined in MVPdma.h
vid_addr_global, // destination address 0
dma_video_tcnt); // transfer counter register
/*
* Initialising the Audio DMA controller
*/
dma_init(
AUDIO_DMA,
dma_audio_prim_ctrl,
dma_audio_sec_ctrl,
MCBSP_DRR_ADDR(1),
aud_addr_global,
dma_audio_tcnt);
/*
* Initialising the Serial Data DMA controller
*/
dma_init(
DATA_DMA,
dma_data_prim_ctrl,
dma_data_sec_ctrl,
MCBSP_DRR_ADDR(0),
datarecaddr,
dma_data_tcnt);
/*
* Initialising and starting the Timer 1
*/
TIMER_INIT(1, 0x100, 0x1, 0);
TIMER_START(0);
/*
* Audio -
*
* Enable the receive and transmit registers, and also
* set the frame sync generator to pulse after 8 CLKG pulses.
*/
SET_BIT(MCBSP_SPCR_ADDR(1), RRST);
SET_BIT(MCBSP_SPCR_ADDR(1), XRST);
SET_BIT(MCBSP_SPCR_ADDR(1), FRST);
/*
* Serial Data -
*
* Enable the receive and transmit registers, and also
* set the frame sync generator (not required for external
* functionality).
*/
SET_BIT(MCBSP_SPCR_ADDR(0), RRST);
SET_BIT(MCBSP_SPCR_ADDR(0), XRST);
SET_BIT(MCBSP_SPCR_ADDR(0), FRST);
/*
* Enable the interrupts
*/
INTR_ENABLE(CPU_INT_NMI);
INTR_ENABLE(CPU_INT7);
INTR_ENABLE(CPU_INT8);
INTR_ENABLE(CPU_INT9);
INTR_ENABLE(CPU_INT10);
INTR_GLOBAL_ENABLE(); // sets the GIE in the CSR register
XCTRL0_HIGH(); // Enable interrupt signal generation on the board.
return 0;
}
/*
* refresh_video_DMA() -
*
* This function refreshes the video_DMA control and transfer counter registers.
*/