/*********************************************************************** *M* Modul:         lwmon.cM*M* Content:       LWMON specific U-Boot commands. * * (C) Copyright 2001, 2002 * DENX Software Engineering * Wolfgang Denk, wd@denx.de * All rights reserved. *D* Design:        wd@denx.deC* Coding:        wd@denx.deV* Verification:  dzu@denx.de * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA ***********************************************************************//*---------------------------- Headerfiles ----------------------------*/#include <common.h>#include <mpc8xx.h>#include <commproc.h>#include <i2c.h>#include <command.h>#include <cmd_bsp.h>#include <malloc.h>#include <post.h>#include <linux/types.h>#include <linux/string.h>	/* for strdup *//*------------------------ Local prototypes ---------------------------*/static long int dram_size (long int, long int *, long int);static void kbd_init (void);static int compare_magic (uchar *kbd_data, uchar *str);/*--------------------- Local macros and constants --------------------*/#define	_NOT_USED_	0xFFFFFFFF#ifdef CONFIG_MODEM_SUPPORTstatic int key_pressed(void);extern void disable_putc(void);#endif /* CONFIG_MODEM_SUPPORT *//* * 66 MHz SDRAM access using UPM A */const uint sdram_table[] ={#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E)	/*	 * Single Read. (Offset 0 in UPM RAM)	 */	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,	0x1FF5FC47, /* last */	/*	 * SDRAM Initialization (offset 5 in UPM RAM)	 *         * This is no UPM entry point. The following definition uses         * the remaining space to establish an initialization         * sequence, which is executed by a RUN command.	 *	 */		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */	/*	 * Burst Read. (Offset 8 in UPM RAM)	 */	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Single Write. (Offset 18 in UPM RAM)	 */	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Burst Write. (Offset 20 in UPM RAM)	 */	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */					    _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Refresh  (Offset 30 in UPM RAM)	 */	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,	0xFFFFFC84, 0xFFFFFC07, /* last */				_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Exception. (Offset 3c in UPM RAM)	 */	0x7FFFFC07, /* last */		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,#endif#ifdef CFG_MEMORY_7E	/*	 * Single Read. (Offset 0 in UPM RAM)	 */	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */	_NOT_USED_,	/*	 * SDRAM Initialization (offset 5 in UPM RAM)	 *         * This is no UPM entry point. The following definition uses         * the remaining space to establish an initialization         * sequence, which is executed by a RUN command.	 *	 */		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */	/*	 * Burst Read. (Offset 8 in UPM RAM)	 */	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */				 	    _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Single Write. (Offset 18 in UPM RAM)	 */	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */					    _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Burst Write. (Offset 20 in UPM RAM)	 */	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,	0xE1BAFC04, 0x1FF5FC47, /* last */			        _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Refresh  (Offset 30 in UPM RAM)	 */	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,	0xFFFFFC84, 0xFFFFFC07, /* last */				_NOT_USED_, _NOT_USED_,	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,	/*	 * Exception. (Offset 3c in UPM RAM)	 */	0x7FFFFC07, /* last */		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,#endif};/* * Check Board Identity: * *//***********************************************************************F* Function:     int checkboard (void) P*A*Z* *P* Parameters:   noneP*P* Returnvalue:  int - 0 is always returned *Z* Intention:    This function is the checkboard() method implementationZ*               for the lwmon board.  Only a standard message is printed. *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/int checkboard (void){	puts ("Board: Litronic Monitor IV\n");	return (0);}/***********************************************************************F* Function:     long int initdram (int board_type) P*A*Z* *P* Parameters:   int board_typeP*                - Usually type of the board - ignored here.P*P* Returnvalue:  long intP*                - Size of initialized memory *Z* Intention:    This function is the initdram() method implementationZ*               for the lwmon board.Z*               The memory controller is initialized to access theZ*               DRAM. *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/long int initdram (int board_type){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immr->im_memctl;	long int size_b0;	long int size8, size9;	int i;	/*	 * Configure UPMA for SDRAM	 */	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));	memctl->memc_mptpr = CFG_MPTPR;	/* burst length=4, burst type=sequential, CAS latency=2 */	memctl->memc_mar = CFG_MAR;	/*	 * Map controller bank 3 to the SDRAM bank at preliminary address.	 */	memctl->memc_or3 = CFG_OR3_PRELIM;	memctl->memc_br3 = CFG_BR3_PRELIM;	/* initialize memory address register */	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */	/* mode initialization (offset 5) */	udelay (200);				/* 0x80006105 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */	udelay (1);				/* 0x80006130 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);	udelay (1);				/* 0x80006130 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);	udelay (1);				/* 0x80006106 */	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);	memctl->memc_mamr |= MAMR_PTBE;	/* refresh enabled */	udelay (200);	/* Need at least 10 DRAM accesses to stabilize */	for (i = 0; i < 10; ++i) {		volatile unsigned long *addr =			(volatile unsigned long *) SDRAM_BASE3_PRELIM;		unsigned long val;		val = *(addr + i);		*(addr + i) = val;	}	/*	 * Check Bank 0 Memory Size for re-configuration	 *	 * try 8 column mode	 */	size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);	udelay (1000);	/*	 * try 9 column mode	 */	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);	if (size8 < size9) {		/* leave configuration at 9 columns */		size_b0 = size9;		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;		udelay (500);	} else {			/* back to 8 columns            */		size_b0 = size8;		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;		udelay (500);	}	/*	 * Final mapping:	 */	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;	udelay (1000);	return (size_b0);}/***********************************************************************F* Function:     static long int dram_size (long int mamr_value,F*                                          long int *base,F*                                          long int maxsize) P*A*Z* *P* Parameters:   long int mamr_valueP*                - Value for MAMR for the testP*               long int *baseP*                - Base address for the testP*               long int maxsizeP*                - Maximum size to test forP*P* Returnvalue:  long intP*                - Size of probed memory *Z* Intention:    Check memory range for valid RAM. A simple memory testZ*               determines the actually available RAM size betweenZ*               addresses `base' and `base + maxsize'. Some (not all)Z*               hardware errors are detected:Z*                - short between address linesZ*                - short between data lines *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/static long int dram_size (long int mamr_value, long int *base, long int maxsize){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	volatile memctl8xx_t *memctl = &immr->im_memctl;	volatile long int *addr;	ulong cnt, val;	ulong save[32];				/* to make test non-destructive */	unsigned char i = 0;	memctl->memc_mamr = mamr_value;	for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {		addr = base + cnt;		/* pointer arith! */		save[i++] = *addr;		*addr = ~cnt;	}	/* write 0 to base address */	addr = base;	save[i] = *addr;	*addr = 0;	/* check at base address */	if ((val = *addr) != 0) {		*addr = save[i];		return (0);	}	for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {		addr = base + cnt;		/* pointer arith! */		val = *addr;		*addr = save[--i];		if (val != (~cnt)) {			return (cnt * sizeof (long));		}	}	return (maxsize);}/* ------------------------------------------------------------------------- */#ifndef	PB_ENET_TENA# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */#endif/***********************************************************************F* Function:     int board_pre_init (void) P*A*Z* *P* Parameters:   noneP*P* Returnvalue:  intP*                - 0 is always returned. *Z* Intention:    This function is the board_pre_init() method implementationZ*               for the lwmon board.Z*               Disable Ethernet TENA on Port B. *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/int board_pre_init (void){	volatile immap_t *immr = (immap_t *) CFG_IMMR;	/* Disable Ethernet TENA on Port B	 * Necessary because of pull up in COM3 port.	 *	 * This is just a preliminary fix, intended to turn off TENA	 * as soon as possible to avoid noise on the network. Once	 * I睠 is running we will make sure the interface is	 * correctly initialized.	 */	immr->im_cpm.cp_pbpar &= ~PB_ENET_TENA;	immr->im_cpm.cp_pbodr &= ~PB_ENET_TENA;	immr->im_cpm.cp_pbdat &= ~PB_ENET_TENA;	/* set to 0 = disabled */	immr->im_cpm.cp_pbdir |= PB_ENET_TENA;	return (0);}/* ------------------------------------------------------------------------- *//***********************************************************************F* Function:     void reset_phy (void) P*A*Z* *P* Parameters:   noneP*P* Returnvalue:  none *Z* Intention:    Reset the PHY.  In the lwmon case we do this by theZ*               signaling the PIC I/O expander. *D* Design:       wd@denx.deC* Coding:       wd@denx.deV* Verification: dzu@denx.de ***********************************************************************/void reset_phy (void){	uchar c;#ifdef DEBUG	printf ("### Switch on Ethernet for SCC2 ###\n");#endif	c = pic_read (0x61);#ifdef DEBUG	printf ("Old PIC read: reg_61 = 0x%02x\n", c);#endif	c |= 0x40;					/* disable COM3 */	c &= ~0x80;					/* enable Ethernet */	pic_write (0x61, c);#ifdef DEBUG	c = pic_read (0x61);	printf ("New PIC read: reg_61 = 0x%02x\n", c);#endif	udelay (1000);}/*------------------------- Keyboard controller -----------------------*//* command codes */#define	KEYBD_CMD_READ_KEYS	0x01#define KEYBD_CMD_READ_VERSION	0x02#define KEYBD_CMD_READ_STATUS	0x03#define KEYBD_CMD_RESET_ERRORS	0x10/* status codes */#define KEYBD_STATUS_MASK	0x3F#define	KEYBD_STATUS_H_RESET	0x20#define KEYBD_STATUS_BROWNOUT	0x10#define KEYBD_STATUS_WD_RESET	0x08#define KEYBD_STATUS_OVERLOAD	0x04#define KEYBD_STATUS_ILLEGAL_WR	0x02#define KEYBD_STATUS_ILLEGAL_RD	0x01/* Number of bytes returned from Keyboard Controller */#define KEYBD_VERSIONLEN	2	/* version information */#define	KEYBD_DATALEN		9	/* normal key scan data *//* maximum number of "magic" key codes that can be assigned */static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;static uchar *key_match (uchar *);#define	KEYBD_SET_DEBUGMODE	'#'	/* Magic key to enable debug output *//***********************************************************************F* Function:     int board_postclk_init (void) P*A*Z* *P* Parameters:   noneP*P* Returnvalue:  intP*                - 0 is always returned. *Z* Intention:    This function is the board_postclk_init() method implementationZ*               for the lwmon board. * ***********************************************************************/int board_postclk_init (void){	DECLARE_GLOBAL_DATA_PTR;	kbd_init();#ifdef CONFIG_MODEM_SUPPORT	if (key_pressed()) {		disable_putc();	/* modem doesn't understand banner etc */		gd->do_mdm_init = 1;	}#endif	return (0);}static void kbd_init (void){	DECLARE_GLOBAL_DATA_PTR;	uchar kbd_data[KEYBD_DATALEN];	uchar tmp_data[KEYBD_DATALEN];	uchar val, errcd;	int i;	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);		gd->kbd_status = 0;	/* Read initial keyboard error code */	val = KEYBD_CMD_READ_STATUS;	i2c_write (kbd_addr, 0, 0, &val, 1);	i2c_read (kbd_addr, 0, 0, &errcd, 1);	/* clear unused bits */	errcd &= KEYBD_STATUS_MASK;	/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */	errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);	if (errcd) {		gd->kbd_status |= errcd << 8;