/* * PCI Express PCI Hot Plug Driver * * Copyright (C) 1995,2001 Compaq Computer Corporation * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) * Copyright (C) 2001 IBM Corp. * Copyright (C) 2003-2004 Intel Corporation * * All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or (at * your option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT.  See the GNU General Public License for more * details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com> * */#include <linux/kernel.h>#include <linux/module.h>#include <linux/types.h>#include <linux/pci.h>#include <linux/interrupt.h>#include "../pci.h"#include "pciehp.h"#ifdef DEBUG#define DBG_K_TRACE_ENTRY      ((unsigned int)0x00000001)	/* On function entry */#define DBG_K_TRACE_EXIT       ((unsigned int)0x00000002)	/* On function exit */#define DBG_K_INFO             ((unsigned int)0x00000004)	/* Info messages */#define DBG_K_ERROR            ((unsigned int)0x00000008)	/* Error messages */#define DBG_K_TRACE            (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)#define DBG_K_STANDARD         (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)/* Redefine this flagword to set debug level */#define DEBUG_LEVEL            DBG_K_STANDARD#define DEFINE_DBG_BUFFER     char __dbg_str_buf[256];#define DBG_PRINT( dbg_flags, args... )              \	do {                                             \	  if ( DEBUG_LEVEL & ( dbg_flags ) )             \	  {                                              \	    int len;                                     \	    len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \		  __FILE__, __LINE__, __FUNCTION__ );    \	    sprintf( __dbg_str_buf + len, args );        \	    printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \	  }                                              \	} while (0)#define DBG_ENTER_ROUTINE	DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");#define DBG_LEAVE_ROUTINE	DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");#else#define DEFINE_DBG_BUFFER#define DBG_ENTER_ROUTINE#define DBG_LEAVE_ROUTINE#endif				/* DEBUG */struct ctrl_reg {	u8 cap_id;	u8 nxt_ptr;	u16 cap_reg;	u32 dev_cap;	u16 dev_ctrl;	u16 dev_status;	u32 lnk_cap;	u16 lnk_ctrl;	u16 lnk_status;	u32 slot_cap;	u16 slot_ctrl;	u16 slot_status;	u16 root_ctrl;	u16 rsvp;	u32 root_status;} __attribute__ ((packed));/* offsets to the controller registers based on the above structure layout */enum ctrl_offsets {	PCIECAPID	=	offsetof(struct ctrl_reg, cap_id),	NXTCAPPTR	=	offsetof(struct ctrl_reg, nxt_ptr),	CAPREG		=	offsetof(struct ctrl_reg, cap_reg),	DEVCAP		=	offsetof(struct ctrl_reg, dev_cap),	DEVCTRL		=	offsetof(struct ctrl_reg, dev_ctrl),	DEVSTATUS	=	offsetof(struct ctrl_reg, dev_status),	LNKCAP		=	offsetof(struct ctrl_reg, lnk_cap),	LNKCTRL		=	offsetof(struct ctrl_reg, lnk_ctrl),	LNKSTATUS	=	offsetof(struct ctrl_reg, lnk_status),	SLOTCAP		=	offsetof(struct ctrl_reg, slot_cap),	SLOTCTRL	=	offsetof(struct ctrl_reg, slot_ctrl),	SLOTSTATUS	=	offsetof(struct ctrl_reg, slot_status),	ROOTCTRL	=	offsetof(struct ctrl_reg, root_ctrl),	ROOTSTATUS	=	offsetof(struct ctrl_reg, root_status),};static int pcie_cap_base = 0;		/* Base of the PCI Express capability item structure */ #define PCIE_CAP_ID(cb)	( cb + PCIECAPID )#define NXT_CAP_PTR(cb)	( cb + NXTCAPPTR )#define CAP_REG(cb)	( cb + CAPREG )#define DEV_CAP(cb)	( cb + DEVCAP )#define DEV_CTRL(cb)	( cb + DEVCTRL )#define DEV_STATUS(cb)	( cb + DEVSTATUS )#define LNK_CAP(cb)	( cb + LNKCAP )#define LNK_CTRL(cb)	( cb + LNKCTRL )#define LNK_STATUS(cb)	( cb + LNKSTATUS )#define SLOT_CAP(cb)	( cb + SLOTCAP )#define SLOT_CTRL(cb)	( cb + SLOTCTRL )#define SLOT_STATUS(cb)	( cb + SLOTSTATUS )#define ROOT_CTRL(cb)	( cb + ROOTCTRL )#define ROOT_STATUS(cb)	( cb + ROOTSTATUS )#define hp_register_read_word(pdev, reg , value)		\	pci_read_config_word(pdev, reg, &value)#define hp_register_read_dword(pdev, reg , value)		\	pci_read_config_dword(pdev, reg, &value) #define hp_register_write_word(pdev, reg , value)		\	pci_write_config_word(pdev, reg, value)#define hp_register_dwrite_word(pdev, reg , value)		\	pci_write_config_dword(pdev, reg, value)/* Field definitions in PCI Express Capabilities Register */#define CAP_VER			0x000F#define DEV_PORT_TYPE		0x00F0#define SLOT_IMPL		0x0100#define MSG_NUM			0x3E00/* Device or Port Type */#define NAT_ENDPT		0x00#define LEG_ENDPT		0x01#define ROOT_PORT		0x04#define UP_STREAM		0x05#define	DN_STREAM		0x06#define PCIE_PCI_BRDG		0x07#define PCI_PCIE_BRDG		0x10/* Field definitions in Device Capabilities Register */#define DATTN_BUTTN_PRSN	0x1000#define DATTN_LED_PRSN		0x2000#define DPWR_LED_PRSN		0x4000/* Field definitions in Link Capabilities Register */#define MAX_LNK_SPEED		0x000F#define MAX_LNK_WIDTH		0x03F0/* Link Width Encoding */#define LNK_X1		0x01#define LNK_X2		0x02#define LNK_X4		0x04	#define LNK_X8		0x08#define LNK_X12		0x0C#define LNK_X16		0x10	#define LNK_X32		0x20/*Field definitions of Link Status Register */#define LNK_SPEED	0x000F#define NEG_LINK_WD	0x03F0#define LNK_TRN_ERR	0x0400#define	LNK_TRN		0x0800#define SLOT_CLK_CONF	0x1000/* Field definitions in Slot Capabilities Register */#define ATTN_BUTTN_PRSN	0x00000001#define	PWR_CTRL_PRSN	0x00000002#define MRL_SENS_PRSN	0x00000004#define ATTN_LED_PRSN	0x00000008#define PWR_LED_PRSN	0x00000010#define HP_SUPR_RM_SUP	0x00000020#define HP_CAP		0x00000040#define SLOT_PWR_VALUE	0x000003F8#define SLOT_PWR_LIMIT	0x00000C00#define PSN		0xFFF80000	/* PSN: Physical Slot Number *//* Field definitions in Slot Control Register */#define ATTN_BUTTN_ENABLE		0x0001#define PWR_FAULT_DETECT_ENABLE		0x0002#define MRL_DETECT_ENABLE		0x0004#define PRSN_DETECT_ENABLE		0x0008#define CMD_CMPL_INTR_ENABLE		0x0010#define HP_INTR_ENABLE			0x0020#define ATTN_LED_CTRL			0x00C0#define PWR_LED_CTRL			0x0300#define PWR_CTRL			0x0400/* Attention indicator and Power indicator states */#define LED_ON		0x01#define LED_BLINK	0x10#define LED_OFF		0x11/* Power Control Command */#define POWER_ON	0#define POWER_OFF	0x0400/* Field definitions in Slot Status Register */#define ATTN_BUTTN_PRESSED	0x0001#define PWR_FAULT_DETECTED	0x0002#define MRL_SENS_CHANGED	0x0004#define PRSN_DETECT_CHANGED	0x0008#define CMD_COMPLETED		0x0010#define MRL_STATE		0x0020#define PRSN_STATE		0x0040static spinlock_t hpc_event_lock;DEFINE_DBG_BUFFER		/* Debug string buffer for entire HPC defined here */static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */static int ctlr_seq_num = 0;	/* Controller sequence # */static spinlock_t list_lock;static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);/* This is the interrupt polling timeout function. */static void int_poll_timeout(unsigned long lphp_ctlr){	struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;	DBG_ENTER_ROUTINE	if ( !php_ctlr ) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return;	}	/* Poll for interrupt events.  regs == NULL => polling */	pcie_isr( 0, (void *)php_ctlr, NULL );	init_timer(&php_ctlr->int_poll_timer);	if (!pciehp_poll_time)		pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/	start_int_poll_timer(php_ctlr, pciehp_poll_time);  		return;}/* This function starts the interrupt polling timer. */static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds){	if (!php_ctlr) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return;	}	if ( ( seconds <= 0 ) || ( seconds > 60 ) )        	seconds = 2;            /* Clamp to sane value */	php_ctlr->int_poll_timer.function = &int_poll_timeout;	php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr;    /* Instance data */	php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;	add_timer(&php_ctlr->int_poll_timer);	return;}static int pcie_write_cmd(struct slot *slot, u16 cmd){	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;	int retval = 0;	u16 slot_status;	DBG_ENTER_ROUTINE 		if (!php_ctlr) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return -1;	}	retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);	if (retval) {			err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);			return retval;		}		if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) { 		/* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue 		   the next command according to spec.  Just print out the error message */		dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);	}	retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);	if (retval) {		err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);		return retval;	}	DBG_LEAVE_ROUTINE 	return retval;}static int hpc_check_lnk_status(struct controller *ctrl){	struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;	u16 lnk_status;	int retval = 0;	DBG_ENTER_ROUTINE 	if (!php_ctlr) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return -1;	}		retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);	if (retval) {		err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);		return retval;	}	dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);	if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) || 		!(lnk_status & NEG_LINK_WD)) {		err("%s : Link Training Error occurs \n", __FUNCTION__);		retval = -1;		return retval;	}	DBG_LEAVE_ROUTINE 	return retval;}static int hpc_get_attention_status(struct slot *slot, u8 *status){	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;	u16 slot_ctrl;	u8 atten_led_state;	int retval = 0;		DBG_ENTER_ROUTINE 	if (!php_ctlr) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return -1;	}	retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);	if (retval) {		err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);		return retval;	}	dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);	atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;	switch (atten_led_state) {	case 0:		*status = 0xFF;	/* Reserved */		break;	case 1:		*status = 1;	/* On */		break;	case 2:		*status = 2;	/* Blink */		break;	case 3:		*status = 0;	/* Off */		break;	default:		*status = 0xFF;		break;	}	DBG_LEAVE_ROUTINE 	return 0;}static int hpc_get_power_status(struct slot * slot, u8 *status){	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;	u16 slot_ctrl;	u8 pwr_state;	int	retval = 0;		DBG_ENTER_ROUTINE 	if (!php_ctlr) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return -1;	}	retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);	if (retval) {		err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);		return retval;	}	dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);	pwr_state = (slot_ctrl & PWR_CTRL) >> 10;	switch (pwr_state) {	case 0:		*status = 1;		break;	case 1:		*status = 0;			break;	default:		*status = 0xFF;		break;	}	DBG_LEAVE_ROUTINE 	return retval;}static int hpc_get_latch_status(struct slot *slot, u8 *status){	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;	u16 slot_status;	int retval = 0;	DBG_ENTER_ROUTINE 	if (!php_ctlr) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return -1;	}	retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);	if (retval) {		err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);		return retval;	}	*status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;  	DBG_LEAVE_ROUTINE 	return 0;}static int hpc_get_adapter_status(struct slot *slot, u8 *status){	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;	u16 slot_status;	u8 card_state;	int retval = 0;	DBG_ENTER_ROUTINE 	if (!php_ctlr) {		err("%s: Invalid HPC controller handle!\n", __FUNCTION__);		return -1;	}	retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);	if (retval) {		err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);		return retval;	}	card_state = (u8)((slot_status & PRSN_STATE) >> 6);	*status = (card_state == 1) ? 1 : 0;	DBG_LEAVE_ROUTINE 	return 0;}static int hpc_query_power_fault(struct slot * slot){	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;	u16 slot_status;	u8 pwr_fault;	int retval = 0;	DBG_ENTER_ROUTINE 	if (!php_ctlr) {