/***SYNCOMS WDT Control Registers */
sfr WDTKEY	= 0x97 ;
sfr WDTC    = 0x9F ;
sfr SCONF   = 0xBF ;

/*********************************
**	SYNCOMS_TYPE  0: NO WDTKEY
**  			  1: HAVE WDTKEY
*********************************/
#define	SYNCOMS_TYPE	0

/*
sbit WDTE   = WDTC^7 ;
sbit CLEAR  = WDTC^5 ;
sbit PS2    = WDTC^2 ;
sbit PS1    = WDTC^1 ;
sbit PS0    = WDTC^0 ;
sbit WDR    = SCONF^7 ;
sbit ALEI   = SCONF^0 ;
*/
/*  8954A  WDTKEY  $97H

By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to
enable the WDTC write attribute, That is
	MOV WDTKEY, # 1EH
	MOV WDTKEY, # E1H
When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to disable the
WDTC write attribute, That is
	MOV WDTKEY, # E1H
	MOV WDTKEY, # 1EH
*/
/************************************************************
Watch Dog Timer Registers- WDT Control Register( WDTC,$9F)

WDTC Registers
	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
	WDTE	Unused	CLEAR	Unused	Unused	PS2		PS1		PS0		R/W
	0		-		0		-		-		0		0		0		Reset value

note:
	WDTE : Watch Dog Timer enable bit
	CLEAR : Watch Dog Timer reset bit
	If CLEAR bit set to1, Watch Dog Timer will be reset. 
	User don’t reset value to 0 .
	
PS2~PS0:clock soure divider bit
	PS [2:0] Divider(OSC in) 	Time Period (ms) @40MHZ
	000 		8 					13.1
	001 		16 					26.21
	010		 	32 					52.42
	011 		64 					104.8
	100 		128 				209.71
	101 		256 				419.43
	110 		512 				838.86
	111 		1024 				1677.72

PS[2:0] 	Timer Period (ms)  @250KHZ
000 		2.048
001 		4.096
010 		8.192
011 		16.384
100 		32.768
101 		65.536
110 		131.072
111 		262.144

Watch Dog Timer Register - System Control Register (SCONF, $BFH)

	bit7	bit6	bit5	bit4	bit3	bit2	bit1	bit0
	WDTE	Unused	Unused	Unused	Unused	Unused	Unused	ALEI	R/W
	0		-		-		-		-		-		-		0		Reset value

note:
	WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
	ALEI : ALE output inhibit bit, to reduce EMI
	The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated
	by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
	
	The SM8951A/8952A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register.
	This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This finction is available 
	when there is no external program memory or no external data RAM in the system.
*****************************************************************/

void SyncomsWDT_Init()
{
#if SYNCOMS_TYPE == 1
	WDTKEY = 0x1E ;		//enable WDTC write
	WDTKEY = 0xE1 ;
	WDTC = WDTC|0x86 ;		//enable WDT soure divider 128	Time Period 
	WDTKEY = 0xE1 ;		//disable WDTC write
	WDTKEY = 0x1E ;
#else
	WDTC = WDTC|0x81 ;		//enable WDT soure divider 8	Time Period 
#endif
}

void SyncomsCLRWDT()	//Clear	WDT
{
#if SYNCOMS_TYPE == 1
	WDTKEY = 0x1E ;		//enable WDTC write
	WDTKEY = 0xE1 ;
#endif
	WDTC = WDTC|0x20 ;	//Clear WDT
#if SYNCOMS_TYPE == 1
	WDTKEY = 0xE1 ;		//disable WDTC write
	WDTKEY = 0x1E ;
#endif
}
/*
#define SyncomsWDT_Init()	WDTC=0x81			//enable WDT soure divider 8
#define SyncomsCLRWDT()		WDTC=0x81|0x20		//Clear	WDT

uchar IsWDT_Rst()		//Is not wdt reset? ;
{
	if((SCONF&0x80) == 1)
	{
		SCONF = SCONF&0x7F ;
		SyncomsWDT_Init() ;
		return TRUE ;
	}
	SyncomsWDT_Init() ;
	return FALSE ;
}*/