?? arm7tdmis_top.vhd
字號:
--****************************************************************************************************
-- Top entity for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 05.02.2003
--****************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use WORK.ARMPackage.all;
entity ARM7TDMIS_Top is port(
-- Clock
CLK : in std_logic;
CLKEN : in std_logic;
-- Interrupts
nRESET : in std_logic;
nIRQ : in std_logic;
nFIQ : in std_logic;
-- Bus control
CFGBIGEND : in std_logic;
-- Arbitration
DMORE : out std_logic;
LOCK : out std_logic;
-- Memory interface
ADDR : out std_logic_vector(31 downto 0);
WDATA : out std_logic_vector(31 downto 0);
RDATA : in std_logic_vector(31 downto 0);
ABORT : in std_logic;
WRITE : out std_logic;
SIZE : out std_logic_vector(1 downto 0);
PROT : out std_logic_vector(1 downto 0);
TRANS : out std_logic_vector(1 downto 0);
-- Memory management interface
CPnTRANS : out std_logic;
CPnOPC : out std_logic;
-- Coprocessor interface
CPnMREQ : out std_logic;
CPnSEQ : out std_logic;
CPTBIT : out std_logic;
CPnI : out std_logic;
CPA : in std_logic;
CPB : in std_logic
);
end ARM7TDMIS_Top;
architecture Struct of ARM7TDMIS_Top is
constant CSlackEstimationCompilation : boolean := TRUE;
-- Components
-- ALU
component ALU is port (
ADataIn : in std_logic_vector(31 downto 0);
BDataIn : in std_logic_vector(31 downto 0);
DataOut : out std_logic_vector(31 downto 0);
InvA : in std_logic;
InvB : in std_logic;
PassA : in std_logic;
PassB : in std_logic; -- MOV/MVN operations
-- Logic operations
AND_Op : in std_logic;
ORR_Op : in std_logic;
EOR_Op : in std_logic;
-- Flag inputs
CFlagIn : in std_logic;
CFlagUse : in std_logic; -- ADC/SBC/RSC instructions
-- Flag outputs
CFlagOut : out std_logic;
VFlagOut : out std_logic;
NFlagOut : out std_logic;
ZFlagOut : out std_logic
);
end component;
-- Shifter
component Shifter is port (
ShBBusIn : in std_logic_vector(31 downto 0); -- Input data (B-Bus)
ShOut : out std_logic_vector(31 downto 0); -- Output data
ShCFlagIn : in std_logic; -- Input of the carry flag
ShCFlagOut : out std_logic; -- Output of the carry flag
ShLenRs : in std_logic_vector(7 downto 0); -- Shift amount for register shift (value of Rs[7..0])
ShLenImm : in std_logic_vector(4 downto 0); -- Shift amount for immediate shift (bits [11..7])
ShType : in std_logic_vector(2 downto 0); -- Shift type (bits 6,5 and 4 of instruction)
ShRotImm : in std_logic; -- Rotate immediate 8-bit value
ShEn : in std_logic;
ShCFlagEn : in std_logic
);
end component;
-- Multiplier
component Multiplier is port (
-- Global signals
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- Data inputs
ADataIn : in std_logic_vector(31 downto 0); -- RdHi(Rn)/Rs data path
BDataIn : in std_logic_vector(31 downto 0); -- RdLo(Rd)/Rm data path
-- Data outputs
ADataOut : out std_logic_vector(31 downto 0);
BDataOut : out std_logic_vector(31 downto 0);
-- Control inputs
LoadRsRm : in std_logic; -- Load Rs and Rm and start
LoadPS : in std_logic; -- Load partial sum register with RHi:RLo
ClearPSC : in std_logic; -- Clear prtial sum register
UnsignedMul : in std_logic; -- Unsigned multiplication
ReadLH : in std_logic; -- 0 - Read PS/PC low,1 - Read PS/PC high
-- Control outputs
MulResRdy : out std_logic -- Multiplication result is ready
);
end component;
-- Register file
component RegFile is generic(DebugMode : boolean);
port(
-- Global control signals
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- Data buses
ABusOut : out std_logic_vector(31 downto 0);
BBusOut : out std_logic_vector(31 downto 0);
DataIn : in std_logic_vector(31 downto 0);
-- Address an control
ABusRdAdr : in std_logic_vector(3 downto 0);
BBusRdAdr : in std_logic_vector(3 downto 0);
WriteAdr : in std_logic_vector(3 downto 0);
WrEn : in std_logic;
-- Program counter
PCIn : in std_logic_vector(31 downto 0);
PCOut : out std_logic_vector(31 downto 0);
PCWrEn : in std_logic; --???
PCSrcSel : in std_logic;
-- Global control
RFMode : in std_logic_vector(4 downto 0);
SaveBaseReg : in std_logic;
RestoreBaseReg : in std_logic
);
end component;
-- Program status registers
component PSR is port(
-- Global control signals
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- ALU Data in
DataIn : in std_logic_vector(31 downto 0);
PSRDInSel : in std_logic;
-- Current program state
CPSRIn : in std_logic_vector(31 downto 0);
CPSRWrEn : in std_logic_vector(31 downto 0);
CPSROut : out std_logic_vector(31 downto 0);
CFlForMul : in std_logic;
-- Saved program state
SPSRIn : in std_logic_vector(31 downto 0);
SPSROut : out std_logic_vector(31 downto 0);
SPSRWrMsk : in std_logic_vector(3 downto 0);
-- PSR mode control
PSRMode : in std_logic_vector(4 downto 0)
);
end component;
-- Instruction pipeline, data in register, immediate data extractor
component IPDR is port(
-- Clock and reset
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- Memory interface
RDATA : in std_logic_vector(31 downto 0);
ABORT : in std_logic;
-- Thumb decoder interface
ToThumbDecoder : out std_logic_vector(31 downto 0);
FromThumbDecoder : in std_logic_vector(31 downto 0);
HalfWordAddress : out std_logic;
-- Interfaces for the internal CPU modules
InstForDecode : out std_logic_vector(31 downto 0);
InstFetchAbort : out std_logic;
ADDRLow : in std_logic_vector(1 downto 0); -- Address [1..0]
StagnatePipeline : in std_logic;
StagnatePipelineDel : in std_logic;
FirstInstFetch : in std_logic;
-- Data out register and control(sign/zero, byte/halfword extension)
DataOut : out std_logic_vector(31 downto 0);
SignExt : in std_logic;
ZeroExt : in std_logic;
nB_HW : in std_logic;
-- Immediate fields out
SExtOffset24Bit : out std_logic_vector(31 downto 0);
Offset12Bit : out std_logic_vector(31 downto 0);
Offset8Bit : out std_logic_vector(31 downto 0);
Immediate8Bit : out std_logic_vector(31 downto 0);
-- Bus control
EndianMode : in std_logic
);
end component;
-- Address register and incrementer
component AddressMux_Incrementer is port(
-- Clock and reset
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- Address and control
ADDR : out std_logic_vector(31 downto 0);
FromPC : in std_logic_vector(31 downto 0);
ToPC : out std_logic_vector(31 downto 0);
FromALU : in std_logic_vector(31 downto 0);
ExceptionVector : in std_logic_vector(31 downto 0);
PCInSel : in std_logic;
ALUInSel : in std_logic;
ExceptionVectorSel : in std_logic;
PCIncStep : in std_logic;
AdrIncStep : in std_logic;
AdrToPCSel : in std_logic;
AdrCntEn : in std_logic
);
end component;
-- Data out register
component DataOutMux is port(
-- Control signals
StoreHalfWord : in std_logic;
StoreByte : in std_logic;
BigEndianMode : in std_logic;
-- Data signals
DataIn : in std_logic_vector(31 downto 0);
WDATA : out std_logic_vector(31 downto 0)
);
end component;
-- Register for shift amount
component ShiftAmountReg is port(
-- Clock and reset
nRESET : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
-- Data signals
ShLenRsIn : in std_logic_vector(7 downto 0); -- Shift amount for register shift (value of Rs[7..0])
ShLenRsOut : out std_logic_vector(7 downto 0)
);
end component;
-- A bus multiplexer
component ABusMultiplexer is port(
-- Data input
RegFileAOut : in std_logic_vector(31 downto 0);
MultiplierAOut : in std_logic_vector(31 downto 0);
CPSROut : in std_logic_vector(31 downto 0);
SPSROut : in std_logic_vector(31 downto 0);
-- Control
RegFileAOutSel : in std_logic;
MultiplierAOutSel : in std_logic;
CPSROutSel : in std_logic;
SPSROutSel : in std_logic;
-- Data output
ABusOut : out std_logic_vector(31 downto 0)
);
end component;
-- B bus multiplexer
component BBusMultiplexer is port(
-- Data input
RegFileBOut : in std_logic_vector(31 downto 0);
MultiplierBOut : in std_logic_vector(31 downto 0);
MemDataRegOut : in std_logic_vector(31 downto 0);
AdrGenDataOut : in std_logic_vector(31 downto 0);
-- Immediate fields
SExtOffset24Bit : in std_logic_vector(31 downto 0);
Offset12Bit : in std_logic_vector(31 downto 0);
Offset8Bit : in std_logic_vector(31 downto 0);
Immediate8Bit : in std_logic_vector(31 downto 0);
-- Control
RegFileBOutSel : in std_logic; -- Output of the register file
MultiplierBOutSel : in std_logic; -- Output of the multiplier
MemDataRegOutSel : in std_logic; -- Output of the data in register
SExtOffset24BitSel : in std_logic;
Offset12BitSel : in std_logic;
Offset8BitSel : in std_logic;
Immediate8BitSel : in std_logic;
AdrGenDataSel : in std_logic;
-- Data output
BBusOut : out std_logic_vector(31 downto 0) -- Connected to the input of the shifter
);
end component;
-- Address generator for load/store
component LSAdrGen is port (
-- Global control signals
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