#include "f2407_c.h"
//#include "math.h"
//#include "stdio.h"
#define Nvecs 200         // the nummber of the vectors
#define PI 3.1415926
#define Ma 0.7       // the scale of the modulating  Ma=3^(0.5)A/Ud
#define Pr_T1   1500    // the period of T1
#define DETA  2*PI/Nvecs
unsigned char vects[]={0x1666,0x3666,0x2666,0x6666,0x4666,0x5666};
unsigned char sect;   // which section the vector located.
int T0,T1,T2;
float SETA=0;   


void initDSP(void)
{
  /* state registers ST0 ST1
  INTM: interrupt mask bit,1- masked ,0-unmasked. after the reset and enter the isr
        it is set to 1.
  OVM:  overflow mode  0-overflow the right way
  CNF:  0:DARAM(B0)-data space
  SXM:  symbol extend mode , 1-symbol extend
  */ 
  asm(" SETC INTM");
  asm(" CLRC CNF"); //B0-data space
  SCSR1 = 0x02ed;
 /*
 bit 15 0: reserved
 bit 14 0: CLKOUT = CPUCLK   1:CLKOUT = WDCLK
 bit 13–12 00: IDLE1 selected for low–power mode
 bit 11–9 001: 000--PLLx4 001--PLL x2 mode                  15M*2 =30M
 bit 8 0: reserved
 bit 7 1: 1/0 = enable/disable ADC module clock =1
 bit 6 1: 1/0 = enable/disable SCI module clock =1
 bit 5 1: 1/0 = enable/disable SPI module clock  =1
 bit 4 0: 1/0 = enable/disable CAN module clock =0
 bit 3 1: 1/0 = enable/disable EVB module clock =1
 bit 2 1: 1/0 = enable/disable EVA module clock =1
 bit 1 0: reserved
 bit 0 1: clear the ILLADR bit
 */
 //SCSR2 = (SCSR2 | 0x002a)&0x002e;//  一或一與即賦予相同的值,巧妙地保留了MP/MC復(fù)位時的狀態(tài)
 SCSR2 = 0x002e ;
 /*
 bit 15–7 0’s: reserved
 bit 6 0: cap1-6,XINT1,XINT2,ADCSOC,PDPNTA/B signals need 5(11)CPUCLKS at least.
 bit 5 1: clear the WD OVERRIDE bit,WD can be disabled by the software
 bit 4 0: XMIF_HI–Z, 0=normal mode, 1=Hi–Z’d
 bit 3 1: disable the boot ROM, enable the FLASH
 bit 2 no change MP/MC* bit reflects state of MP/MC* pin
 bit 1:0  10 = SARAM mapped to data
 */
  WDCR = 0x006f;
 /*
 bits 15–8 0’s: reserved
 bit 7 0: clear WD flag
 bit 6 1: disable the dog
 bit 5–3 101: must be written as 101
 bit 2–0 000: WDCLK divider = 1 ,111-->209ms  (40M)
*/
IFR&=0XFFFF; // clear all the int flags(write the IFR to IFR)
IMR=0x0000; // all the ints are masked
/*by the way,after reset,all the peripheral interrupt 
flag and mask registers are cleared, interrupts are forbidened*/
WSGR = 0x0108;//0x00c8;//0x0088;//0x0089;
 /*
 bit 15–11 0’s: reserved
 bit 10–9 00: bus visibility off
 bit 8–6 100: 4 wait–state for I/O space
 bit 5–3 001: 1 wait–state for data space
 bit 2–0 000: 0 wait state for program space
 */
}
void F24x_WD_ResetCounter(void)
{
    
        WDKEY=0x5555;                  /* Reset WDog   */
        WDKEY=0xaaaa;
}
void F24x_WD_Disable(void)
{
        WDCR=0x006f;                /* Write Control Register to Disable Watchdog */
}

void initSVPWM1(void)
{
  ACTRA=0x1666;
  COMCONA=(COMCONA|0x9200)&0x9300;
}

int sectFind(void)
{
  int i;
  if(SETA>=2*PI) {SETA-=2*PI; i=0;}
  else if(SETA>=5*PI/3)i=5;
  else if(SETA>=4*PI/3)i=4;
  else if(SETA>=3*PI/3)i=3;
  else if(SETA>=2*PI/3)i=2;
  else if(SETA>=1*PI/3)i=1;
  else i=0;
  return(i);	
}
interrupt void T1DwnFlw_isr(void)
{
  if(PIVR=0x0029)
    {SETA+=DETA;    
     sect=sectFind();
     ACTRA=vects[sect];
     T1=(int)Ma*2*Pr_T1*sin(PI/3-SETA);
     T2=(int)Ma*2*Pr_T1*sin(SETA);
     CMPR1=(int)T1/2;
     CMPR2=(int)(T1+T2)/2;
     asm(" clrc INTM");
     EVAIFRA=EVAIFRA&0XFFFF;     
    }
   else{ asm(" clrc INTM");EVAIFRA=EVAIFRA&0XFFFF;}
}
 interrupt void nothing(void)
 {
   	asm(" clrc INTM");
 }

void main(void)
{
 
 
 //ACTRA=0x1666;
 // COMCONA=(COMCONA|0x9200&0x9300;
 initDSP();
 initSVPWM1();
 
 T1=(int)Ma*2*Pr_T1*sin(PI/3);
 T2=0;
 sect=sectFind();
 ACTRA=vects[sect];
 CMPR1=(int)T1/2;
 CMPR2=(int)(T1+T2)/2;
 T1CNT=0x0578;
 T1CON=0x0840;
asm(" clrc INTM");
IMR|=0x0002;
EVAIMRA|=0X0200; 
 while(1){F24x_WD_ResetCounter();}
}