library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity daccontrol is
    Port ( fudu:in std_logic_vector(7 downto 0);
           dac_fudu:out std_logic_vector(7 downto 0));
end daccontrol;

architecture Behavioral of daccontrol is
signal mids:std_logic_vector(7 downto 0) ;
begin
process(fudu) is
 begin
 case fudu is
 when "00000001" =>mids<="00110011";
 when "00000010" =>mids<="01100110";
 when "00000011" =>mids<="10011001";
 when "00000100" =>mids<="11001100";
 when others =>mids<="11111111";
 end case;
end process;
dac_fudu<=mids;
end Behavioral;