#ifndef cpu_hh_included#define cpu_hh_included#include "inttypes.hh"#include "clock.hh"#include "module.hh"#include "simarg.hh"#include "serial.hh"#include "interruptsink.hh"// CPU adds fetch-execute loop support to Module.class CPU    : public virtual Serializable, public Module, public Clock, public InterruptSink{private:    // The scheduler information (see "sulima/cpu.cc").    static int cpu_count;    static CPU *first_cpu, *last_cpu;    CPU *next_cpu;protected:    // Timeslice of this CPU.    // Do not change or you're wreck havoc in the scheduler!!!    ClockValue timeslice;    // Minimum and maximum timeslice. Adjust these if needed.    static const ClockValue min_timeslice = 32;    static const ClockValue max_timeslice = 16*KB;public:    // An interrupt event.    class InterruptEvent	: public virtual Serializable, public Event    {    private:	static SerialType<InterruptEvent> type;	CPU* cpu;	Int8 num;    public:	InterruptEvent(Int8 n, CPU* c, ClockValue when)	    : Event(when), cpu(c), num(n) { }	explicit InterruptEvent(const SimArgs& args)	    : Event(args) { assert(UNREACHABLE); }	explicit InterruptEvent(Checkpoint& cp);	void invoke();	void checkpoint(Checkpoint& cp, bool parent = false) const;    };    // Dump state for debugging    virtual void dump_state() = 0;    // Constructors, etc.    CPU(const char *n, ClockValue f);    explicit CPU(const SimArgs &args);    explicit CPU(Checkpoint &cp);    void checkpoint(Checkpoint &cp, bool parent = false) const;    // Simulator interfaces.    virtual void run(ClockValue timeslice) = 0;    // Tcl interfaces.    static SimArg run_all(const SimArgs &args);    Int32 trace_level;};#endif // cpu_hh_included